Simultaneous molecular beam deposition of monocrystalline and polycrystalline III(a)-V(a) compounds to produce semiconductor devices

Claim 1

A METHOD OF FABRICATING PLANAR ISOLATED SEMICONDUCTOR DEVICES COMPRISING THE STEPS OF: A. FORMING AN AMORPHOUS INSULATIVE LAYER ON A MAJOR SURFACE OF A SUBSTRATE COMPRISING A COMPOUND OF A GROUP III(A)V(A) MATERIAL; SAID SUBSTRATE BEING AT LEAST SEMI-INSULATING; B. REMOVING SELECTED PORTIONS OF SAID AMORPHOUS LAYER TO FORM A PLURALITY OF WINDOWS WHICH EXPOSE THE UNDERLYING SUBSTRATE; C. PLACING SAID SUBSTRATE IN AN EVACUABLE CHAMBER; D. REDUCING THE PRESSURE OF SAID CHAMBER TO A SUBATMOSPHERIC PRESSURE; E. PREHEATING SAID SUBSTRATE TO A TEMPERATURE IN THE RANGE OF 450* TO 675*C APPROXIMATELY; AND F. DIRECTING AT LEAST ONE MOLECULAR BEAM COMPRISING AT LEAST ONE GROUP III(A) ELEMENT AND AT LEAST ONE GROUP V(A) ELEMENT AT SAID MAJOR SURFACE SO THAT MONOCRYSTALLINE MATERIAL COMPRISING A COMPOUND OF SAID ELEMENTS IS DEPOSITED IN SAID WINDOWS AND ON SAID SUBSTRATE AND SIMULTANEOUSLY POLYCRYSTALLINE MATERIAL COMPRISING THE SAME COMPOUND OF SAID ELEMENTS IS DEPOSITED ON SAID AMORPHOUS LAYER, SAID POLYCRYSTALLINE MATERIAL BEING OF SUFFICIENTLY HIGH RESISTIVITY TO PRODUCE ELECTRICAL ISOLATION BETWEEN SAID DEVICES FORMED IN SEPARATE ONES OF SAID WINDOWS AND BEING SUBSTANTIALLY COPLANAR WITH SAID MONOCRYSTALLINE MATERIAL.

Claim 2

A METHOD OF FABRICATING PLANAR ISOLATED SEMICONDUCTOR DEVICES COMPRISING THE STEPS OF: A. FORMING AN AMORPHOUS INSULATIVE LAYER ON A MAJOR SURFACE OF A SUBSTRATE COMPRISING A COMPOUND OF A GROUP III(A)V(A) MATERIAL; SAID SUBSTRATE BEING AT LEAST SEMI-INSULATING; B. REMOVING SELECTED PORTIONS OF SAID AMORPHOUS LAYER TO FORM A PLURALITY OF WINDOWS WHICH EXPOSE THE UNDERLYING SUBSTRATE; C. PLACING SAID SUBSTRATE IN AN EVACUABLE CHAMBER; D. REDUCING THE PRESSURE OF SAID CHAMBER TO A SUBATMOSPHERIC PRESSURE; E. PREHEATING SAID SUBSTRATE TO A TEMPERATURE IN THE RANGE OF 450* TO 675*C APPROXIMATELY; AND F. DIRECTING AT LEAST ONE MOLECULAR BEAM COMPRISING AT LEAST ONE GROUP III(A) ELEMENT AND AT LEAST ONE GROUP V(A) ELEMENT AT SAID MAJOR SURFACE SO THAT MONOCRYSTALLINE MATERIAL COMPRISING A COMPOUND OF SAID ELEMENTS IS DEPOSITED IN SAID WINDOWS AND ON SAID SUBSTRATE AND SIMULTANEOUSLY POLYCRYSTALLINE MATERIAL COMPRISING THE SAME COMPOUND OF SAID ELEMENTS IS DEPOSITED ON SAID AMORPHOUS LAYER, SAID POLYCRYSTALLINE MATERIAL BEING OF SUFFICIENTLY HIGH RESISTIVITY TO PRODUCE ELECTRICAL ISOLATION BETWEEN SAID DEVICES FORMED IN SEPARATE ONES OF SAID WINDOWS AND BEING SUBSTANTIALLY COPLANAR WITH SAID MONOCRYSTALLINE MATERIAL.

Claim 14

A method of fabricating planar isolated semiconductor devices from materials containing compounds including Ga and As comprising the steps of: a. forming an amorphous insulative layer on a major surface of a semi-insulating GaAs substrate, said insulative layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride and native oxides; b. removing selected portions of said insulative layer to form a plurality of windows which expose portions of the underlying substrate; c. placing said substrate in an evacuable chamber and reducing the background pressure of said chamber to at least 10 6 Torr approximately; d. just prior to step (e) preheating said substrate to a temperature in the range of 450* to 675* C under condition of excess As pressure at said surface; e. directing at least one first molecular beam comprising Ga, As and the dopant upon said surface to deposit a monocrystalline GaAs buffer layer in said windows and on said substrate and simultaneously to deposit a relatively high resistivity polycrystalline GaAs first layer on said insulative layer; f. directing at least one second molecular beam comprising a Group III(a) element, a Group V(a) element and a dopant element upon said buffer layer and said polycrystalline layer for a time period sufficient to effect growth of a second monocrystalline GaAs layer on said buffer layer and a second polycrystalline GaAs layer on said first polycrystalline layer; g. maintaining the relative proportion of the constitutents of said first and second molecular beams so that at the growth surface there is an excess of Group V(a) elements with respect to Group III(a) elements; and h. beginning with step (e) and until said buffer layer and all layers of said device are deposited, maintaining the deposition process continuous.

Claim 15

A method of fabricating planar isolated semiconductor devices from materials containing compounds including Ga and As comprising the steps of: a. forming an amorphous insulative layer on a major surface of a semi-insulating GaAs substrate, said insulative layer comprising a material selected from the group consisting of silicon dioxide, silicon nitride and native oxides; b. removing selected portions of said insulative layer to form a plurality of windows which expose portions of the underlying substrate; c. placing said substrate in an evacuable chamber and reducing the background pressure of said chamber to at least 10 6 Torr approximately; d. just prior to step (e) preheating said substrate to a temperature in the range of 450* to 675* C under condition of excess As pressure at said surface; e. directing at least one first molecular beam comprising Ga, As and the dopant upon said surface to deposit a monocrystalline GaAs buffer layer in said windows and on said substrate and simultaneously to deposit a relatively high resistivity polycrystalline GaAs first layer on said insulative layer; f. directing at least one second molecular beam comprising a Group III(a) element, a Group V(a) element and a dopant element upon said buffer layer and said polycrystalline layer for a time period sufficient to effect growth of a second monocrystalline GaAs layer on said buffer layer and a second polycrystalline GaAs layer on said first polycrystalline layer; g. maintaining the relative proportion of the constitutents of said first and second molecular beams so that at the growth surface there is an excess of Group V(a) elements with respect to Group III(a) elements; and h. beginning with step (e) and until said buffer layer and all layers of said device are deposited, maintaining the deposition process continuous.