Patent US4636269A successfully refreshed from Google Patents.
US4636269A
Expired / Lapsed
US
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Epitaxially isolated semiconductor device process utilizing etch and refill technique
Assignee: Motorola Solutions Inc
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Filing: 1985-07-02
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Granted: 1987-01-13
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Expires: 2005-07-02
Abstract
Abstract A process is disclosed for manufacturing electrically isolated semiconductor device structures. The process includes the steps of providing a semiconductor substrate and selectively etching one surface of that substrate to form etched regions and unetched regions. In a single epitaxial growth step three separate epitaxial layers are grown overlying both the etched and unetched regions. The epitaxial layers are then shaped back to form a substantially planar surface and to expose portions of the first epitaxial layer. The exposed portion of the first epitaxial layer, in combination with the substrate, is suitable for the fabrication of a back contact power transistor. The second epitaxial layer, which follows the contour of the etched surface, bends upwardly and intersects the planar surface to substantially surround portions of the third epitaxial layer and to electrically isolate those portions of the third epitaxial layer from the substrate and first epitaxial layer. The portions of the third epitaxial layer are thus suitable for the implementation of an integrated control circuit function.
Inventors
- 👤 Bernard W. Boland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:17
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/30; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10W10/01; H10W10/031; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/05; Y10S148/085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
71 words
A process for manufacturing electrically isolated semiconductor device structures comprising the steps of: providing a semiconductor substrate having a surface; selectively etching portions of said surface to form etched regions and unetched regions; epitaxially forming first, second and third layers overlying said etched and unetched regions; and shaping back said epitaxial layer to form a substantially planar surface and to expose a portion of said first layer overlying said unetched region.
Claim 2
Dependent Claim
71 words
A process for manufacturing electrically isolated semiconductor device structures comprising the steps of: providing a semiconductor substrate having a surface; selectively etching portions of said surface to form etched regions and unetched regions; epitaxially forming first, second and third layers overlying said etched and unetched regions; and shaping back said epitaxial layer to form a substantially planar surface and to expose a portion of said first layer overlying said unetched region.
Claim 3
Dependent Claim
27 words
The process of claim 1 wherein said substrate, first and third layers are of a first conductivity type and said second layer is of opposite conductivity type.
Claim 4
Dependent Claim
153 words
A process for manufacturing electrically isolated semiconductor device structures comprising the steps of: providing a silicon substrate of first conductivity type and resistivity; forming an etch mask on a surface of said substrate, said mask having openings therethrough to expose portions of said surface; etching exposed portions of said surface to form etched regions having mesa-like unetched portions extending upwardly therefrom; forming a first epitaxial layer of said first conductivity type and of higher resistivity overlying said substrate; forming a second epitaxial layer of opposite conductivity type overlying said first epitaxial layer; forming a third epitaxial layer of said first conductivity type overlying said second epitaxial layer; shaping back said epitaxial layers to form a planar surface and to expose a portion of said first epitaxial layer overlying said unetched region; fabricating device regions in said exposed portion of said first epitaxial layer; and fabricating control circuit functions in said third epitaxial layer.
Claim 5
Dependent Claim
153 words
A process for manufacturing electrically isolated semiconductor device structures comprising the steps of: providing a silicon substrate of first conductivity type and resistivity; forming an etch mask on a surface of said substrate, said mask having openings therethrough to expose portions of said surface; etching exposed portions of said surface to form etched regions having mesa-like unetched portions extending upwardly therefrom; forming a first epitaxial layer of said first conductivity type and of higher resistivity overlying said substrate; forming a second epitaxial layer of opposite conductivity type overlying said first epitaxial layer; forming a third epitaxial layer of said first conductivity type overlying said second epitaxial layer; shaping back said epitaxial layers to form a planar surface and to expose a portion of said first epitaxial layer overlying said unetched region; fabricating device regions in said exposed portion of said first epitaxial layer; and fabricating control circuit functions in said third epitaxial layer.
Claim 6
Dependent Claim
31 words
The process of claim 3 wherein said step of etching is continued to a predetermined depth and said second and third epitaxial layers have a combined thickness greater than said depth.
Claim 7
Dependent Claim
21 words
The process of claim 3 wherein said first, second, and third epitaxial layers are formed in a single epitaxial growth process.
Claim 8
Dependent Claim
15 words
The process of claim 3 wherein said step of shaping back comprises lapping and polishing.
Claim 9
Dependent Claim
81 words
A process for fabricating a semiconductor device which comprises the steps of: providing a silicon substrate having a surface; selectively etching portions of said surface to a predetermined depth; forming a plurality of epitaxial layers of alternating conductivity type overlying said surface, each of said layers having a predetermined conductivity type and thickness, the first of said layers contacting said substrate; shaping back said epitaxial layers to expose a portion of said first epitaxial layer overlying unetched portions of said surface.
Claim 10
Dependent Claim
81 words
A process for fabricating a semiconductor device which comprises the steps of: providing a silicon substrate having a surface; selectively etching portions of said surface to a predetermined depth; forming a plurality of epitaxial layers of alternating conductivity type overlying said surface, each of said layers having a predetermined conductivity type and thickness, the first of said layers contacting said substrate; shaping back said epitaxial layers to expose a portion of said first epitaxial layer overlying unetched portions of said surface.
Claim 11
Dependent Claim
19 words
The process of claim 7 wherein said plurality of epitaxial layers are formed in s single epitaxial growth process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-12 | 1990-07-14 | 1991-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-12 | 1994-07-14 | 1995-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-12 | 1998-07-14 | 1999-01-13 | $7700.00 | Window Closed / Lapsed |