US3566220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated semiconductor circuit having complementary transistors provided with dielectric isolation and surface collector contacts
Assignee: Texas Instruments Inc
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Filing: 1969-04-25
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Granted: 1971-02-23
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Expires: 1989-04-25
Abstract
Abstract An integrated semiconductor circuit wherein the functional electronic components are separated by dielectric isolation and is provided with complementary transistors, each having a buried heavily doped collector contact region extending to the upper surface of the semiconductor slice. The structure provides each transistor with a low collector saturation resistance, and permits all ohmic contacts to be made at the same surface of the slice.
Inventors
- 👤 Simon D Post
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:04
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/05; Y10S148/051; Y10S148/085
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
13 words
A semiconductor device as defined by claim 1 wherein said semiconductor is silicon.
Claim 2
Dependent Claim
30 words
A semiconductor device as defined by claim 1 wherein said first plurality of semiconductor layers are of PNP conductivity and said second plurality of semiconductor layers are of NPN conductivity.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |