US3853644A
Expired / Lapsed
US
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Transistor for super-high frequency and method of manufacturing it
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1972-09-07
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Granted: 1974-12-10
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Expires: 1992-09-07
Abstract
Abstract An insulated gate field effect transistor with very small drain capacitance is made by forming as a layer on a substrate of semiconductor material a first region containing impurities of opposite conductivity types with different concentrations and different diffusion characteristics. A recess formed in the first region is filled with semiconductor material by epitaxial growth to form a second region and impurity from the first region is heat diffused into a contiguous portion of the second region to form an intermediate base region the width of which is determined by differences in diffusion distances of the two impurities of opposite type. Also a transistor with a very small collector capacitance is made by masking a surface of a semiconductor body containing impurity of a first conductivity type, forming a window in said mask, hollowing out a recess through the window, partially filling the recess by epitaxial deposit with semiconductor material of the opposite type to form a first region containing a concentration of impurity of the first type with a higher diffusion coefficient than the impurity of the opposite type, epitaxially depositing further material in the recess to form a second region and heat diffusing impurity from said first region into a contiguous portion of said second region to form an intermediate base region the thickness of which is determined by the difference in diffusion distances of the impurities.
Inventors
- 👤 Y Hayashi
- 👤 Y Tarui
- 👤 T Sekigawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D10/00; H10D10/40; H10D10/461; H10D30/01; H10D30/021; H10D30/028; H10D30/64; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/053; Y10S148/151
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
206 words
A METHOD OF MANUFACTURING AN INSULATED GATE FIELD EFFECT TRANSISTOR, WHICH COMPRISES THE STEPS OF: PROVIDING AS A SOURCE REGION A SEMICONDUCTOR BODY OF A FIRST CONDUCTIVITY TYPE OPPOSITE THE FIRST CONDUCTIVITY TYPE, WHICH ARE OPPOSITE IN CONDUCTIVITY TYPE AND DIFFERENT IN CONCENTRATION AND IN DIFFUSIVITY, THE IMPURITY LOWER IN CONCENTRATION HAVING GREATER DIFFUSIVITY AND A SECOND CONDUCTIVITY TYPE OPPOSITE THE FIRST CONDUCTIVITY TYPE, REMOVING A PORTION OF SAID SOURCE REGION TO FORM A RECESS THREIN, FILLING SAID RECESS BY SUCCESSIVE EPITAXIAL GROWTH TO FORM A LIGHTLY DOPED DRAIN REGION OF THE FIRST CONDUCTIVITY TYPE AND A HEAVILY DOPED DRAIN CONTACT REGION OF THE SAME CONDUTIVITY TYPE AS SAID DRAIN REGION, DIFFUSING BY HEAT TREATMENT SAID IMPURITY CONTAINED IN SAID SOURCE REGION AND LOWER IN CONCENTRATION AND HIGHER IN DIFFUSIVITY INTO A PART OF SAID DRAIN REGION ADJACENT TO SAID SOURCE REGION TO FORM A BASE REGION BETWEEN SAID SOURCE AND DRAIN REGIONS, APPLYING A GATE INSULATOR OVER SAID CONDUCTOR BODY AND APPLYING A GATE ELECTRODE OVER SAID INSULATOR, A CHANNEL BEING INDUCED IN THE SURFACE OF SAID BASE REGION BY FIELD APPLIED FROM SAID GATE ELECTRODE THROUGH SAID INSULTOR, THE LENGTH OF SAID CHANNEL BEING DETERMINED ONLY BY THE DIFFUSION LENGTH OF SAID DIFFUSED IMPURITY.
Claim 2
Independent Claim
206 words
A METHOD OF MANUFACTURING AN INSULATED GATE FIELD EFFECT TRANSISTOR, WHICH COMPRISES THE STEPS OF: PROVIDING AS A SOURCE REGION A SEMICONDUCTOR BODY OF A FIRST CONDUCTIVITY TYPE OPPOSITE THE FIRST CONDUCTIVITY TYPE, WHICH ARE OPPOSITE IN CONDUCTIVITY TYPE AND DIFFERENT IN CONCENTRATION AND IN DIFFUSIVITY, THE IMPURITY LOWER IN CONCENTRATION HAVING GREATER DIFFUSIVITY AND A SECOND CONDUCTIVITY TYPE OPPOSITE THE FIRST CONDUCTIVITY TYPE, REMOVING A PORTION OF SAID SOURCE REGION TO FORM A RECESS THREIN, FILLING SAID RECESS BY SUCCESSIVE EPITAXIAL GROWTH TO FORM A LIGHTLY DOPED DRAIN REGION OF THE FIRST CONDUCTIVITY TYPE AND A HEAVILY DOPED DRAIN CONTACT REGION OF THE SAME CONDUTIVITY TYPE AS SAID DRAIN REGION, DIFFUSING BY HEAT TREATMENT SAID IMPURITY CONTAINED IN SAID SOURCE REGION AND LOWER IN CONCENTRATION AND HIGHER IN DIFFUSIVITY INTO A PART OF SAID DRAIN REGION ADJACENT TO SAID SOURCE REGION TO FORM A BASE REGION BETWEEN SAID SOURCE AND DRAIN REGIONS, APPLYING A GATE INSULATOR OVER SAID CONDUCTOR BODY AND APPLYING A GATE ELECTRODE OVER SAID INSULATOR, A CHANNEL BEING INDUCED IN THE SURFACE OF SAID BASE REGION BY FIELD APPLIED FROM SAID GATE ELECTRODE THROUGH SAID INSULTOR, THE LENGTH OF SAID CHANNEL BEING DETERMINED ONLY BY THE DIFFUSION LENGTH OF SAID DIFFUSED IMPURITY.
Claim 3
Independent Claim
209 words
A method of manufacturing an insulated gate field effect transistor which comprises the steps of forming as a layer on a substrate of semiconductor material which contains an impurity of a first conductivity type, a first region containing an impurity having a high diffusion characteristic of the same type as said substrate anD an impurity of the opposite conductivity type having a high concentration and low diffusion characteristic, providing a mask over said first region, providing a window in said mask, forming through said first region a recess to expose said substrate through said window, successively depositing in said recess by epitaxial growth through said window lightly doped second and heavily doped third regions of semiconductor material of said opposite conductivity type, said third region being isolated from said first region by said second region, effecting by heat diffusion a diffusion of impurity of said first conductivity type from said first region into said second region to form between said first and second regions a base region the width of which is determined by the difference in diffusion of said impurities of said first conductivity type and said second conductivity type, applying a gate insulator over said first and third region and applying a gate electrode over said insulator.
Claim 4
Independent Claim
209 words
A method of manufacturing an insulated gate field effect transistor which comprises the steps of forming as a layer on a substrate of semiconductor material which contains an impurity of a first conductivity type, a first region containing an impurity having a high diffusion characteristic of the same type as said substrate anD an impurity of the opposite conductivity type having a high concentration and low diffusion characteristic, providing a mask over said first region, providing a window in said mask, forming through said first region a recess to expose said substrate through said window, successively depositing in said recess by epitaxial growth through said window lightly doped second and heavily doped third regions of semiconductor material of said opposite conductivity type, said third region being isolated from said first region by said second region, effecting by heat diffusion a diffusion of impurity of said first conductivity type from said first region into said second region to form between said first and second regions a base region the width of which is determined by the difference in diffusion of said impurities of said first conductivity type and said second conductivity type, applying a gate insulator over said first and third region and applying a gate electrode over said insulator.
Claim 5
Independent Claim
234 words
A method of manufacturing a transistor, which comprises the steps of providing a mask on a surface of a semiconductor body containing an impurity of a first conductivity type, forming a window in said mask, hollowing out a recess in said body by a selective photoengraving process through said window, partially filling said recess by epitaxial growth through said window with semiconductor material of the opposite conductivity type to form a first region containing a, small impurity concentration of said first impurity type with a higher diffusion coefficient than that of said opposite impurity type, additionally depositing in said recess by epitaxial growth through said window semiconductor material of said opposite opposite conductivity type with an impurity concentration less than that of said first impurity type in said first region, further depositing on said second region by epitaxial growth through said window semiconductor material of said opposite conductivity type to form a third region having a larger impurity concentration than that of said second region, and effecting by a heat diffusion process a diffusion of impurity of said first conductivity type from said first region into said second region to form between said first and second regions a base region, the width of which is determined by the difference of the diffusion distances of said impurity of said first conductivity type contained in said first region and said impurity of said opposite conductivity type.
Claim 6
Independent Claim
234 words
A method of manufacturing a transistor, which comprises the steps of providing a mask on a surface of a semiconductor body containing an impurity of a first conductivity type, forming a window in said mask, hollowing out a recess in said body by a selective photoengraving process through said window, partially filling said recess by epitaxial growth through said window with semiconductor material of the opposite conductivity type to form a first region containing a, small impurity concentration of said first impurity type with a higher diffusion coefficient than that of said opposite impurity type, additionally depositing in said recess by epitaxial growth through said window semiconductor material of said opposite opposite conductivity type with an impurity concentration less than that of said first impurity type in said first region, further depositing on said second region by epitaxial growth through said window semiconductor material of said opposite conductivity type to form a third region having a larger impurity concentration than that of said second region, and effecting by a heat diffusion process a diffusion of impurity of said first conductivity type from said first region into said second region to form between said first and second regions a base region, the width of which is determined by the difference of the diffusion distances of said impurity of said first conductivity type contained in said first region and said impurity of said opposite conductivity type.
Claim 7
Dependent Claim
30 words
A method according to claim 3, further comprising diffusing impurity of said first conductive type into an exposed edge portion of said base region to provide a base electrode contact.
Claim 8
Independent Claim
236 words
A method of manufacturing an insulated field effect transistor comprising: a. providing as a source region a semiconductor substrate of first conductivity type containing two impurities of opposite conductivity type and different concentrations and diffusivities, the impurity having the second conductivity type opposite the first conductivity type being lower in concentration and having a greater diffusivity than the impurity having the first conductivity type; b. forming on said substrate a lightly doped drain region of the first conductivity type and on said drain region a heavily doped drain contact region of the first conductivity type by successive epitaxial growth; c. heating said substrate to effect diffusion of the second conductivity type impurity from said substrate into said drain region to form a base region therebetween; said base region having a width determined by the difference in diffusion of said first and second conductivity type impurities. d. removing portions of said drain contact, drain, base and source regions and exposing a surface of said source region by selective etching so that remaining portions of said drain contact, drain and base regions and the underlying portion of said source region form a protrusion extending above the surface of said source region, said drain contact, Drain, base and source regions being exposed along lateral surfaces of said protrusion; e. disposing a gate insulator overlying the surfaces of said protrusion; and f. disposing a gate electrode overlying said gate insulator.
Claim 9
Independent Claim
236 words
A method of manufacturing an insulated field effect transistor comprising: a. providing as a source region a semiconductor substrate of first conductivity type containing two impurities of opposite conductivity type and different concentrations and diffusivities, the impurity having the second conductivity type opposite the first conductivity type being lower in concentration and having a greater diffusivity than the impurity having the first conductivity type; b. forming on said substrate a lightly doped drain region of the first conductivity type and on said drain region a heavily doped drain contact region of the first conductivity type by successive epitaxial growth; c. heating said substrate to effect diffusion of the second conductivity type impurity from said substrate into said drain region to form a base region therebetween; said base region having a width determined by the difference in diffusion of said first and second conductivity type impurities. d. removing portions of said drain contact, drain, base and source regions and exposing a surface of said source region by selective etching so that remaining portions of said drain contact, drain and base regions and the underlying portion of said source region form a protrusion extending above the surface of said source region, said drain contact, Drain, base and source regions being exposed along lateral surfaces of said protrusion; e. disposing a gate insulator overlying the surfaces of said protrusion; and f. disposing a gate electrode overlying said gate insulator.
References Cited (Backward Citations)
US3558375A
Cited
GB1045429A
Cited
US3370995A
Cited
US3511724A
Cited
US3655457A
Cited
US3577045A
Cited
US3740276A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |