Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation

Claim 1

A method for fabricating an array of complementary bipolar transistors in an N-type silicon substrate, comprising the steps of: ion implanting a first plurality of P-type regions relatively deeply beneath the surface of said substrate, a first subplurality thereof forming the subcollectors of PNP transistors and a second subplurality thereof forming the intrinsic base region of NPN transistors; ion implanting a second plurality of P-type regions shallowly beneath the surface of said substrate, each of a first subplurality thereof juxtaposed above and intersecting respective ones of said first subplurality in said first plurality of P-type regions, forming the collector contacts for said PNP transistors and each of a second subplurality thereof juxtaposed above and intersecting respective ones of said second subplurality of said first plurality of P-type regions, forming the extrinsic base region of said NPN transistors; ion implanting a plurality of N-type conductivity base regions in said substrate, each juxtaposed above and intersecting a respective one of said first subplurality of PNP subcollectors, forming the base regions of PNP transistors, said N-type base regions having a dopant concentration at the surface of said substrate of less than 10 17 atoms per cubic centimeter; depositing a plurality of metal contacts having a metal work function of approximately 4.8 electron volts or greater, on the surface of said substrate, each spaced from a respective one of said first subplurality of PNP collector contacts and electrically contacting a respective, corresponding one of said plurality of N-type conductivity base regions, forming a Schottky Barrier emitter for each of said PNP transistors, having a barrier height with a magnitude greater than 0.8 electron volts; ion implanting an N-type dopant as the base contact in said PNP transistors and as the emitter in said NPN transistors; whereby a plurality of PNP bipolar transistors with Schottky Barrier contact emitters is formed simultaneously with a plurality of NPN transistors on the same semiconductor chip.

Claim 2

A method for fabricating an array of complementary bipolar transistors in an N-type silicon substrate, comprising the steps of: ion implanting a first plurality of P-type regions relatively deeply beneath the surface of said substrate, a first subplurality thereof forming the subcollectors of PNP transistors and a second subplurality thereof forming the intrinsic base region of NPN transistors; ion implanting a second plurality of P-type regions shallowly beneath the surface of said substrate, each of a first subplurality thereof juxtaposed above and intersecting respective ones of said first subplurality in said first plurality of P-type regions, forming the collector contacts for said PNP transistors and each of a second subplurality thereof juxtaposed above and intersecting respective ones of said second subplurality of said first plurality of P-type regions, forming the extrinsic base region of said NPN transistors; ion implanting a plurality of N-type conductivity base regions in said substrate, each juxtaposed above and intersecting a respective one of said first subplurality of PNP subcollectors, forming the base regions of PNP transistors, said N-type base regions having a dopant concentration at the surface of said substrate of less than 10 17 atoms per cubic centimeter; depositing a plurality of metal contacts having a metal work function of approximately 4.8 electron volts or greater, on the surface of said substrate, each spaced from a respective one of said first subplurality of PNP collector contacts and electrically contacting a respective, corresponding one of said plurality of N-type conductivity base regions, forming a Schottky Barrier emitter for each of said PNP transistors, having a barrier height with a magnitude greater than 0.8 electron volts; ion implanting an N-type dopant as the base contact in said PNP transistors and as the emitter in said NPN transistors; whereby a plurality of PNP bipolar transistors with Schottky Barrier contact emitters is formed simultaneously with a plurality of NPN transistors on the same semiconductor chip.