US4183036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky-transistor-logic
Assignee: Siemens AG
•
Filing: 1977-05-20
•
Granted: 1980-01-08
•
Expires: 1997-05-20
Abstract
Abstract A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor. A plurality of Schottky diodes are also formed in a portion of the epitaxial layer which possess a lower Schottky barrier than the Schottky electrode of the output transistor.
Inventors
- 👤 Ruediger Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:30
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/652; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D64/00; H10D64/60; H10D64/64; H10D84/611; H10D84/613; H10D84/617
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
Schottky-transistor-logic comprising a highly doped semiconductor substrate of one conductivity type, an epitaxial layer of said one conductivity type on said substrate, a buried layer of the other conductivity type in said epitaxial layer spaced below the outer surface of said epitaxial layer in a plane substantially parallel to said outer surface, an insulating wall extending through said epitaxial layer and into said substrate thereby dividing said epitaxial layer into two zones, a collector and an emitter being provided in one of said zones by portions of said epitaxial layer above and below said buried layer, and a base being provided by said buried layer between said collector and said emitter, a Schottky-transistor being provided in said one zone by a Schottky electrode on the surface of said epitaxial layer, a portion of said epitaxial layer and a portion of said buried layer therebetween, a plurality of additional Schottky electrodes on the surface of said other zone of said epitaxial layer, said plurality of additional Schottky electrodes possessing a lower Schottky-barrier than the output Schottky electrode of said output transistor, and an external contact connecting the two portions of said epitaxial layer lying above said buried layer.
Claim 2
Dependent Claim
197 words
Schottky-transistor-logic comprising a highly doped semiconductor substrate of one conductivity type, an epitaxial layer of said one conductivity type on said substrate, a buried layer of the other conductivity type in said epitaxial layer spaced below the outer surface of said epitaxial layer in a plane substantially parallel to said outer surface, an insulating wall extending through said epitaxial layer and into said substrate thereby dividing said epitaxial layer into two zones, a collector and an emitter being provided in one of said zones by portions of said epitaxial layer above and below said buried layer, and a base being provided by said buried layer between said collector and said emitter, a Schottky-transistor being provided in said one zone by a Schottky electrode on the surface of said epitaxial layer, a portion of said epitaxial layer and a portion of said buried layer therebetween, a plurality of additional Schottky electrodes on the surface of said other zone of said epitaxial layer, said plurality of additional Schottky electrodes possessing a lower Schottky-barrier than the output Schottky electrode of said output transistor, and an external contact connecting the two portions of said epitaxial layer lying above said buried layer.
Claim 3
Dependent Claim
273 words
Schottky-transistor-logic comprising a highly doped semiconductor substrate of one conductivity type, an epitaxial layer of said one conductivity type on said substrate, a buried layer of the other conductivity type in said epitaxial layer spaced below the outer surface of said epitaxial layer in a plane substantially parallel to said outer surface, an insulating wall extending through said epitaxial layer and into said substrate thereby dividing said epitaxial layer into a first zone and a second zone, a load transistor and an output transistor each having a base, a collector and an emitter, the base of said load transistor being provided by the buried layer of said first zone, the collector of said load transistor being provided by the portion of said epitaxial layer of said first zone lying above said buried layer, and the emitter of said load transistor being provided by the portion of said epitaxial layer in said first zone lying below said buried layer, the base of said output transistor being provided by the portion of said epitaxial layer first zone lying above said buried layer, the emitter of said output transistor being provided by said buried layer of said first zone, and the collector of said output transistor being provided by a Schottky electrode on the surface of said epitaxial layer of said first zone, a plurality of additional Schottky electrodes on the surface of said second zone of said epitaxial layer, said plurality of additional Schottky electrodes possessing a lower Schottky-barrier than the output Schottky electrode of said output transistor, and an external contact connecting the two portions of said epitaxial layer lying above said buried layer.
Claim 4
Dependent Claim
273 words
Schottky-transistor-logic comprising a highly doped semiconductor substrate of one conductivity type, an epitaxial layer of said one conductivity type on said substrate, a buried layer of the other conductivity type in said epitaxial layer spaced below the outer surface of said epitaxial layer in a plane substantially parallel to said outer surface, an insulating wall extending through said epitaxial layer and into said substrate thereby dividing said epitaxial layer into a first zone and a second zone, a load transistor and an output transistor each having a base, a collector and an emitter, the base of said load transistor being provided by the buried layer of said first zone, the collector of said load transistor being provided by the portion of said epitaxial layer of said first zone lying above said buried layer, and the emitter of said load transistor being provided by the portion of said epitaxial layer in said first zone lying below said buried layer, the base of said output transistor being provided by the portion of said epitaxial layer first zone lying above said buried layer, the emitter of said output transistor being provided by said buried layer of said first zone, and the collector of said output transistor being provided by a Schottky electrode on the surface of said epitaxial layer of said first zone, a plurality of additional Schottky electrodes on the surface of said second zone of said epitaxial layer, said plurality of additional Schottky electrodes possessing a lower Schottky-barrier than the output Schottky electrode of said output transistor, and an external contact connecting the two portions of said epitaxial layer lying above said buried layer.
Claim 5
Dependent Claim
16 words
Schottky-transistor-logic according to claim 2, in which said insulating wall is formed of SiO 2 .
References Cited (Backward Citations)
US3823353A
Cited
US3922565A
Cited
US3961351A
Cited
US3909807A
Cited
US4035664A
Cited
US3987310A
Cited
US4053925A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-07 | 1983-07-09 | 1984-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-07 | 1987-07-09 | 1988-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-07 | 1991-07-09 | 1992-01-08 | $7700.00 | Window Closed / Lapsed |