Integrated circuit memory cell

Claim 2

A memory cell for an integrated circuit memory comprising: a flip-flop comprising first and second directly cross-coupled memory transistors each having a base, a collector, and an emitter; first and second bit output lines; means coupling said collectors of said first and second memory transistors with said first and second bit output lines respectively; first and second current source transistors each comprising a base, a collector and an emitter, the emitters of said current source transistors connected one to the other and arranged to be connected to a source of potential, the collectors of said first and second current source transistors connected respectively to said bases of said first and second memory transistors; and a word line connected to the emitters of said first and second memory transistors and to the bases of said current source transistors.

Claim 3

A memory cell for an integrated circuit memory in accordance with claim 1 wherein said coupling means comprises first and second Schottky diodes formed at said collectors of said first and second memory transistors.

Claim 4

A memory cell in accordance with claim 1 wherein said first and second memory transistors each comprise a Schottky diode clamped transistor.

Claim 5

A memory cell for an integrated circuit memory comprising two identical halves, each half integrally formed without surface metal interconnections and comprising: an npn memory transistor; a pnp current source transistor having its collector formed integrally with the collector of said memory transistor; a bit line; a Schottky diode formed on the collector of said memory transistor and interconnecting said collector and said bit line; a word line connected directly to the emitter of said memory transistor and to the base of said current source transistor; a power line formed integrally with the emitter of said current source transistor; terminal means for applying a source of potential to said power line; and surface metal interconnecting means cross-connecting the bases and collectors of the memory transistors of two halves to form a flip-flop circuit.

Claim 6

A memory cell for an integrated circuit memory comprising two identical halves, each half integrally formed without surface metal interconnections and comprising: an npn memory transistor; a pnp current source transistor having its collector formed integrally with the collector of said memory transistor; a bit line; a Schottky diode formed on the collector of said memory transistor and interconnecting said collector and said bit line; a word line connected directly to the emitter of said memory transistor and to the base of said current source transistor; a power line formed integrally with the emitter of said current source transistor; terminal means for applying a source of potential to said power line; and surface metal interconnecting means cross-connecting the bases and collectors of the memory transistors of two halves to form a flip-flop circuit.

Claim 7

A memory cell for an integrated circuit memory array comprising: a flip-flop comprising first and second directly cross-coupled Schottky diode clamped transistors; first and second bit output lines; first and second Schottky diodes connected respectively between said first and second bit lines and the collectors of said first and second transistors; first and second current source transistors having their emitters connected one to the other and arranged to be connected to a source of potential and having their collectors connected respectively to said collectors of said first and second cross-coupled transistors; and a word line connected to the emitters of said first and second cross-coupled transistors and to the bases of said current source transistors.

Claim 8

A memory cell for an integrated circuit memory array comprising: a flip-flop comprising first and second directly cross-coupled Schottky diode clamped transistors; first and second bit output lines; first and second Schottky diodes connected respectively between said first and second bit lines and the collectors of said first and second transistors; first and second current source transistors having their emitters connected one to the other and arranged to be connected to a source of potential and having their collectors connected respectively to said collectors of said first and second cross-coupled transistors; and a word line connected to the emitters of said first and second cross-coupled transistors and to the bases of said current source transistors.

Claim 9

An integrated circuit memory formed in a body comprising: a semiconductor substrate wherein a plurality of substantially parallel but spaced apart word lines of one conductivity type are diffused and an epitaxial layer of said one conductivity overlying said substrate, said memory comprising: a plurality of bit lines, said plurality corresponding in number to the number of bits in Each memory word; a plurality of cells for each of said word lines, said plurality of cells corresponding in number to the number of bits in each memory word, each of said cells comprising two interconnected halves, each said half being formed in said body without surface metal interconnections and comprising: a vertical memory transistor formed in a first region of said epitaxial layer defined by a region of the opposite conductivity type extending through said epitaxial layer from the exposed surface thereof to the substrate and encircling said first region, each said memory transistor comprising a collector region of said first conductivity type at the exposed surface of said epitaxial layer an emitter region of said first conductivity type adjacent to the buried surface of said epitaxial layer and a base region of said opposite conductivity type formed by ion implantation in said first region but spaced apart from said exposed and said buried surfaces of said epitaxial layer; a lateral current source transistor formed in said epitaxial layer and comprising: a collector region formed of part of said throughextending region of said opposite conductivity type, an emitter formed of a further throughextending region of said opposite conductivity type spaced apart from but in operational relationship with said first named throughextending region, and a base comprising an active portion of the epitaxial layer intermediate said throughextending regions of said opposite conductivity type; means for applying potential to said second throughextending region of said opposite conductivity type, a Schottky diode formed at the collector of said memory transistor for interconnecting a corresponding bit line to said half, an ohmic connection to said collector of said memory transistor and conductor means for interconnecting said ohmic connection of one cell half to the base of a memory transistor of another half.

Claim 10

An integrated circuit memory formed in a body comprising: a semiconductor substrate wherein a plurality of substantially parallel but spaced apart word lines of one conductivity type are diffused and an epitaxial layer of said one conductivity overlying said substrate, said memory comprising: a plurality of bit lines, said plurality corresponding in number to the number of bits in Each memory word; a plurality of cells for each of said word lines, said plurality of cells corresponding in number to the number of bits in each memory word, each of said cells comprising two interconnected halves, each said half being formed in said body without surface metal interconnections and comprising: a vertical memory transistor formed in a first region of said epitaxial layer defined by a region of the opposite conductivity type extending through said epitaxial layer from the exposed surface thereof to the substrate and encircling said first region, each said memory transistor comprising a collector region of said first conductivity type at the exposed surface of said epitaxial layer an emitter region of said first conductivity type adjacent to the buried surface of said epitaxial layer and a base region of said opposite conductivity type formed by ion implantation in said first region but spaced apart from said exposed and said buried surfaces of said epitaxial layer; a lateral current source transistor formed in said epitaxial layer and comprising: a collector region formed of part of said throughextending region of said opposite conductivity type, an emitter formed of a further throughextending region of said opposite conductivity type spaced apart from but in operational relationship with said first named throughextending region, and a base comprising an active portion of the epitaxial layer intermediate said throughextending regions of said opposite conductivity type; means for applying potential to said second throughextending region of said opposite conductivity type, a Schottky diode formed at the collector of said memory transistor for interconnecting a corresponding bit line to said half, an ohmic connection to said collector of said memory transistor and conductor means for interconnecting said ohmic connection of one cell half to the base of a memory transistor of another half.