US4030083A — Self-refreshed capacitor memory cell

Claim 1

Independent Claim 200 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network means for providing access reading and writing signals to the element; and c. a second electrical network refresh means including first and second switching transistors, each having a pair of high current terminals and a low current terminal, one high current terminal of the first switching transistor being ohmically connected to a terminal of the memory element and the other high current terminal of the first switching transistor being ohmically connected to an electrically conductive refresh line, said refresh line having a refresh terminal means for the connection thereto of electrical means for acting as an electrical sink for spurious charges in the memory element during operation, one high current terminal of the second switching transistor being ohmically connected to the one high current terminal of the first switching transistor and the other high current terminal of the second switching transistor being ohmically connected to the low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a different terminal of the memory element.

Claim 2

Dependent Claim 200 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network means for providing access reading and writing signals to the element; and c. a second electrical network refresh means including first and second switching transistors, each having a pair of high current terminals and a low current terminal, one high current terminal of the first switching transistor being ohmically connected to a terminal of the memory element and the other high current terminal of the first switching transistor being ohmically connected to an electrically conductive refresh line, said refresh line having a refresh terminal means for the connection thereto of electrical means for acting as an electrical sink for spurious charges in the memory element during operation, one high current terminal of the second switching transistor being ohmically connected to the one high current terminal of the first switching transistor and the other high current terminal of the second switching transistor being ohmically connected to the low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a different terminal of the memory element.

Claim 3

Dependent Claim 53 words

Semiconductor apparatus in accordance with claim 1 in which the first and second switching transistors are insulated gate field effect transistors and in which the one and the other high current terminals are source and drain regions in the transistors, and in which the low current terminals are gate electrodes of the transistors.

Claim 4

Dependent Claim 41 words

Apparatus according to claim 2 in which the switching transistors and the capacitor are all integrated in a monocrystalline semiconductor substrate, the gate to drain electrical capacitance of the first switching transistor being less than the capacitance of the memory element.

Claim 5

Dependent Claim 34 words

Apparatus according to claim 3 in which the memory element is a layered structure of an electrically insulating layer sandwiched between a semiconductor layer portion of the semiconductor substrate and an electrically conducting layer.

Claim 6

Dependent Claim 31 words

Apparatus according to claim 4 in which the electrically conducting layer of the memory element is essentially polycrystalline semiconductor which contains electrically significant impurities sufficient to render the layer electrically conductive.

Claim 7

Dependent Claim 31 words

Semiconductor apparatus according to claim 2 in which said refresh terminal means is connected to said electrical means including circuit means for providing an A.C. voltage to said refresh terminal means.

Claim 8

Dependent Claim 36 words

Apparatus according to claim 6 in which said circuit means is such that the A.C. voltage is interruptable to a predetermined voltage level during operation in response to an enable signal applied to said circuit means.

Claim 9

Dependent Claim 23 words

Apparatus according to claim 6 in which the said different terminal of the memory element is for connection to a D.C. voltage source.

Claim 10

Dependent Claim 30 words

Semiconductor apparatus according to claim 3 in which said different terminal of the memory element is connected to circuit means for providing an A.C. voltage to the said different terminal.

Claim 11

Dependent Claim 36 words

Apparatus according to claim 9 in which said circuit means is such that said A.C. voltage is interruptable during operation to a predetermined voltage level in response to an enable signal applied to said circuit means.

Claim 12

Dependent Claim 16 words

Apparatus according to claim 9 in which the said electrical means comprises a D.C. source means.

Claim 13

Dependent Claim 49 words

Apparatus according to claim 2 in which said memory element together with said first and second transistors are integrated in a single semiconductor substrate and which further includes circuit means for the application of an A.C. voltage to said substrate sufficient to pump the spurious charges into the sink.

Claim 14

Dependent Claim 34 words

Apparatus according to claim 12 in which said circuit means is such that said A.C. voltage is interruptable to a predetermined voltage level in response to an enable signal applied to the circuit means.

Claim 15

Dependent Claim 31 words

Apparatus according to claim 12 in which said different terminal of the memory element is for connection to a D.C. source means and said electrical means comprises a D.C. source means.

Claim 16

Dependent Claim 212 words

A semiconductor device which comprises: a. a capacitor memory element capable of storing electrical charge representative of the memory state of the element; b. a gating transistor, one of whose relatively high current carrying terminals is connected to a first terminal of the capacitor element in order to provide read and write signals to the memory state of the memory element in either one of two states; c. a first switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a separate electrically conductive refresh line which is not part of an electrical network for providing said read and write signals to the capacitor element, said refresh line having a refresh terminal means for application thereto of charge sink means for collecting spurious charges in the memory element during operation; d. a second switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a second terminal of the capacitor memory element.

Claim 17

Dependent Claim 212 words

A semiconductor device which comprises: a. a capacitor memory element capable of storing electrical charge representative of the memory state of the element; b. a gating transistor, one of whose relatively high current carrying terminals is connected to a first terminal of the capacitor element in order to provide read and write signals to the memory state of the memory element in either one of two states; c. a first switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a separate electrically conductive refresh line which is not part of an electrical network for providing said read and write signals to the capacitor element, said refresh line having a refresh terminal means for application thereto of charge sink means for collecting spurious charges in the memory element during operation; d. a second switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a second terminal of the capacitor memory element.

Claim 18

Dependent Claim 68 words

Semiconductor apparatus which comprises an array of semiconductor devices, each device in accordance with claim 15, each capacitor memory element being a layered structure essentially of metal-insulator-semiconductor, each of said devices being integrated in a single crystal semiconductor substrate, portions of which substrate serving as the semiconductor layer for each capacitor element, the gating transistor and the first and second switching transistors being insulated gate field effect transistors.

Claim 19

Dependent Claim 176 words

A semiconductor memory cell which comprises: a. an electrical memory storage capacitor containing a portion of a surface region of a semiconductor substrate for charge storage in accordance with electrical signals delivered to said capacitor from an input access network; b. first insulated gate field effect transistor means for draining off spurious charge from the said substrate portion to a voltage source which is connected through a refresh line to the drain of said first transistor, the gate to drain capacitance of the first transistor being smaller than the capacitance of the memory capacitor; and c. a second insulated gate field effect transistor means for controlling the first transistor, the source terminal of the second transistor being connected both to the source terminal of the first transistor and to the substrate portion of the storage capacitor, the gate electrode of the second transistor being connected to a plate of the storage capacitor spaced apart from the said substrate portion, the drain terminal of the second transistor being connected to the gate elecrode of the first transistor.

Claim 20

Dependent Claim 176 words

A semiconductor memory cell which comprises: a. an electrical memory storage capacitor containing a portion of a surface region of a semiconductor substrate for charge storage in accordance with electrical signals delivered to said capacitor from an input access network; b. first insulated gate field effect transistor means for draining off spurious charge from the said substrate portion to a voltage source which is connected through a refresh line to the drain of said first transistor, the gate to drain capacitance of the first transistor being smaller than the capacitance of the memory capacitor; and c. a second insulated gate field effect transistor means for controlling the first transistor, the source terminal of the second transistor being connected both to the source terminal of the first transistor and to the substrate portion of the storage capacitor, the gate electrode of the second transistor being connected to a plate of the storage capacitor spaced apart from the said substrate portion, the drain terminal of the second transistor being connected to the gate elecrode of the first transistor.

Claim 21

Dependent Claim 114 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network for providing access writing and reading signals to the element; c. a second electrical network separate from said first network including a first switching transistor having one of its high current carrying terminals ohmically coupled to a first terminal of the memory element and having another of its high current terminals ohmically coupled to an electrically conductive refresh line for preserving the memory states of the capacitor in the absence of access signals, by collecting spurious charges from said capacitor which are being generated therein during operation.

Claim 22

Dependent Claim 114 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network for providing access writing and reading signals to the element; c. a second electrical network separate from said first network including a first switching transistor having one of its high current carrying terminals ohmically coupled to a first terminal of the memory element and having another of its high current terminals ohmically coupled to an electrically conductive refresh line for preserving the memory states of the capacitor in the absence of access signals, by collecting spurious charges from said capacitor which are being generated therein during operation.

Claim 23

Dependent Claim 78 words

Apparatus according to claim 18, which further includes a second switching transistor having one of its high current carrying terminals ohmically coupled to the first terminal of the memory element and another of its high current carrying terminals ohmically coupled to a low current carrying terminal of the first switching transistor, a low current carrying terminal of the second switching transistor being ohmically coupled to a second terminal of the memory element insulated from the first terminal thereof.

Claim 24

Dependent Claim 90 words

Apparatus according to claim 19 in which the capacitor memory element formed by a layered structure of metal-like, insulator, and semiconductor layers, respectively, which is integrated in a monocrystalline semiconductor substrate, the second switching transistor being an insulated gate field effect transistor having source, gate, and drain regions in said substrate, the said source region of the second switching transistor being provided by a portion of the semiconductor substrate underlying the metal-like layer of the capacitor memory element and bordering on the gate region of the said second switching transistor.

Claim 25

Dependent Claim 11 words

Apparatus according to claim 20, in which the semiconductor is silicon.

Claim 26

Dependent Claim 37 words

Apparatus in accordance with claim 21, in which the said refresh line is connected to circuit means for providing an A.C. voltage of predetermined excursion to said refresh line sufficient to collect said spurious charges during operation.

Claim 27

Dependent Claim 29 words

Apparatus in accordance with claim 22, in which said A.C. voltage is interruptable to a predetermined voltage level in response to an enable signal applied to said circuit means.

Claim 28

Dependent Claim 55 words

Apparatus according to claim 23, in which said substrate has a terminal for the application thereto of a reverse bias voltage for forming a depletion layer in the semiconductor surface portion underneath the metal-like layer during operation and in which said second terminal of the memory element is for connection to a D.C. voltage source.

Claim 29

Dependent Claim 44 words

Apparatus according to claim 21, in which the first terminal of the memory element is connected to circuit means for providing an A.C. voltage to said second terminal of the memory element sufficient to pump said spurious charges into the refresh line during operation.

Claim 30

Dependent Claim 20 words

Apparatus according to claim 25, in which said refresh line has a terminal for connection to a D.C. voltage source.

Claim 31

Dependent Claim 28 words

Apparatus according to claim 26, in which said A.C. voltage is interruptable to a predetermined voltage level in response to an enable signal applied to said circuit means.

Claim 32

Dependent Claim 37 words

Apparatus according to claim 27, in which said substrate has a terminal for the application thereto of a reverse bias voltage for forming a depletion layer in the semiconductor surface portion underneath the metal-like layer during operation.

Claim 33

Dependent Claim 57 words

Apparatus according to claim 21, in which said substrate has a terminal for application thereto of an A.C. voltage with an average voltage level sufficient to form a depletion layer in the semiconductor surface portion underneath the metal-like layer during operation and in which said refresh line has a terminal for connection to a D.C. voltage source.

Claim 34

Dependent Claim 42 words

Apparatus according to claim 29, which further includes circuit means for applying the A.C. voltage to said terminal of the substrate, said A.C. voltage being interruptable to a predetermined voltage level in response to an enable signal applied to said circuit means.

Claim 35

Dependent Claim 22 words

Apparatus according to claim 30, in which the second terminal of the memory element is for connection to a D.C. voltage source.

Claim 36

Dependent Claim 174 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network means for providing access reading and writing signals to the element; and c. a second electrical network refresh means including first and second switching transistors, each having a pair of high current terminals and a low current terminal, one high current terminal of the first switching transistor being connected to a terminal of the memory element and the other high current terminal of the first switching transistor being connected to an electrical refresh line which is not a part of the first network, one high current terminal of the second switching transistor being connected to the one high current terminal of the first switching transistor and the other high current terminal of the second switching transistor being connected to the low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a different terminal of the memory element.

Claim 37

Dependent Claim 174 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network means for providing access reading and writing signals to the element; and c. a second electrical network refresh means including first and second switching transistors, each having a pair of high current terminals and a low current terminal, one high current terminal of the first switching transistor being connected to a terminal of the memory element and the other high current terminal of the first switching transistor being connected to an electrical refresh line which is not a part of the first network, one high current terminal of the second switching transistor being connected to the one high current terminal of the first switching transistor and the other high current terminal of the second switching transistor being connected to the low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a different terminal of the memory element.

Claim 38

Dependent Claim 71 words

The apparatus of claim 32, in which the first and second switching transistors are insulated gate field effect transistors and in which the one and the other high current terminals are source and drain regions in the transistors, and in which the low current terminals are gate electrodes of the transistors; the gate to drain electrical capacitance of the first switching transistor being less than the capacitance of the memory element.

Claim 39

Dependent Claim 32 words

Apparatus according to claim 33, in which the capacitor is integrated in a semiconductor substrate and in which the switching transistors and the capacitor are all integrated in a monocrystalline semiconductor substrate.

Claim 40

Dependent Claim 29 words

Apparatus according to claim 34, in which the memory element is a layered structure of an electrically insulating layer sandwiched between a semiconductor layer and an electrically conducting layer.

Claim 41

Dependent Claim 27 words

Apparatus according to claim 35, in which the electrically conducting layer is essentially polycrystalline semiconductor which contains electrically significant impurities sufficient to render the layer electrically conductive.

Claim 42

Dependent Claim 29 words

Apparatus according to claim 33, in which the refresh line is connected to an A.C. source means for acting as a sink for spurious charges in the memory element.

Claim 43

Dependent Claim 176 words

A semiconductor device which comprises: a. a capacitor memory element capable of storing electrical charge representative of the memory state of the element; b. a gating transistor, one of whose relatively high current carrying terminals is connected to a first terminal of the capacitor element in order to control the memory state of the memory element in one of two states; c. a first switching transistor one of whose high current terminals connected to the said first terminal of the capacitor element and the other of whose high current terminals connected to an electrical refresh line which is not part of an electrical access network for reading and writing access to the capacitor element; d. a second switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a second terminal of the capacitor memory element.

Claim 44

Dependent Claim 176 words

A semiconductor device which comprises: a. a capacitor memory element capable of storing electrical charge representative of the memory state of the element; b. a gating transistor, one of whose relatively high current carrying terminals is connected to a first terminal of the capacitor element in order to control the memory state of the memory element in one of two states; c. a first switching transistor one of whose high current terminals connected to the said first terminal of the capacitor element and the other of whose high current terminals connected to an electrical refresh line which is not part of an electrical access network for reading and writing access to the capacitor element; d. a second switching transistor one of whose high current terminals is connected to the said first terminal of the capacitor element and the other of whose high current terminals is connected to a low current terminal of the first switching transistor, the low current terminal of the second switching transistor being connected to a second terminal of the capacitor memory element.

Claim 45

Dependent Claim 76 words

Semiconductor apparatus which comprises an array of semiconductor devices, each device comprising an MIS layered semiconductor capacitor memory element, a gating transistor, a first switching transistor, and a second switching transistor mutually connected in accordance with claim 39, said device being integrated in a single crystal semiconductor substrate portions of which serving as the semiconductor layer for each capacitor element, the gating transistor and the first and second switching transistors being insulated gate field effect transistors.

Claim 46

Dependent Claim 107 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network for providing access writing and reading signals to the element; c. a second electrical network including a switching transistor having one of its high current carrying terminals D.C. coupled to a first terminal of the memory element and having another of its high current terminals D.C. coupled to a refresh line for preserving the memory states of the capacitor in the absence of access signals, said line having a terminal means for the application of an A.C. voltage source thereto.

Claim 47

Dependent Claim 107 words

Apparatus which comprises: a. a capacitor memory element capable of storing electrical charge to represent binary digital memory states of the element; b. a first electrical network for providing access writing and reading signals to the element; c. a second electrical network including a switching transistor having one of its high current carrying terminals D.C. coupled to a first terminal of the memory element and having another of its high current terminals D.C. coupled to a refresh line for preserving the memory states of the capacitor in the absence of access signals, said line having a terminal means for the application of an A.C. voltage source thereto.

Claim 48

Dependent Claim 78 words

Apparatus according to claim 40, which further includes a second switching transistor having one of its high current carrying terminals D.C. coupled to the first terminal of the memory element and another of its high current carrying terminals D.C. coupled to a low current carrying terminal of the first switching transistor, a low current carrying terminal of the second switching transistor being D.C. coupled to a second terminal of the memory element insulated from the first terminal thereof.

Claim 49

Dependent Claim 89 words

Apparatus according to claim 41, in which the capacitor memory element formed by a layered structure of metal-like, insulator, and semiconductor layers which is integrated in a monocrystalline semiconductor substrate, the second switching transistor being an insulated gate field effect transistor having source, gate, and drain regions in said substrate the said source region of the second switching transistor being provided by a portion of the semiconductor substrate underlying the metal-like layer of the capacitor memory element and bordering on the gate region of the said second switching transistor.

Claim 50

Dependent Claim 11 words

Apparatus according to claim 42, in which the semiconductor is silicon.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-06-13	1980-12-13	1981-06-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-06-13	1984-12-13	1985-06-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-06-13	1988-12-13	1989-06-14	$7700.00	Window Closed / Lapsed

Self-refreshed capacitor memory cell

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