Random access memory cell

Claim 2

Storage means comprising a storage node having capacitance, a second node having capacitance, an intermittent voltage source, first and second switching means connecting the voltage source to the second node, the first switching means being controlled by the voltage on the storage node, the second switching means being controlled by first recurring clock pulses, a third switching means connecting the second node to the storage node, the third switching means being controlled by second recurring clock pulses out of phase with the first clock pulses.

Claim 3

Storage means according to claim 1 wherein the second node is connected to means for writing in and reading out data.

Claim 4

Storage means according to claim 2 wherein the second node is connected to the means for writing in and reading out data via a fourth switching means which is controlled by an address signal.

Claim 5

Storage means according to claim 1 wherein the first and second recurring clock pulses are non-overlapping.

Claim 6

Storage means according to claim 4 wherein the intermittent voltage source is the same as the first source of recurring clock signals.

Claim 7

Storage means according to claim 5 wherein the second node is connected to means for writing in and reading out logic levels via a fourth switching means which is controlled by an address signal.

Claim 8

Storage means according to claim 6 wherein the address signal subsists during the first recurring clock signals for reading out and during the secoond recurring clock signals for writing in.

Claim 9

Storage means according to claim 7 wherein the switching means are insulated gate field effect transistors.

Claim 10

Storage means according to claim 8 wherein at least part of the capacitance of the storage node is an MOS transistor across the first switching means.

Claim 11

A memory cell comprising first and second sources of recurring clock signals, a first field effect transistor having a current path connected between a voltage supply and a source node, a second field effect transistor having a current path connected between the refresh node and a storage node, the gate of the second field effect transsistor being connected to the first source of clock pulses, transistor gate of the third transistor being connected to the second source of clock signals, and means for reading out and writing in logic levels to the refresh node.

Claim 12

A memory cell comprising first and second sources of recurring clock signals, a first field effect transistor having a current path connected between a voltage supply and a source node, a second field effect transistor having a current path connected between the refresh node and a storage node, the gate of the second field effect transsistor being connected to the first source of clock pulses, transistor gate of the third transistor being connected to the second source of clock signals, and means for reading out and writing in logic levels to the refresh node.

Claim 13

A memory cell according to claim 10 wherein said voltage supply is the first source of clock signals.

Claim 14

A memory cell according to claim 11 wherein the means for reading out and writing in comprises a fourth field effect transistor having a current path connected between the refresh mode and a source of data.

Claim 15

A memory cell according to claim 12 wherein the gate of the fourth field effect transistor is driven by address signals which are on during the first clock signals for reading out and on during the second clock signals for writing in.

Claim 16

A memory cell according to claim 13 wherein the storage node includes capacitance existing between the storage node and the source node.

Claim 17

A memory cell according to claim 14 wherein said capacitance includes an MOS capacitor.

Claim 18

A memory cell according to claim 14 wherein said capacitance includes a voltage-dependent MOS capacitor device.

Claim 19

A memory cell according to claim 11 wherein an MOS capacitor is provided between said storage node and the first source of clock signals.

Claim 20

A self-refreshing memory cell for a random access memory system comprising first and second capacitance means, a plurality of switching means each having a current path and a control means for controlling current through the current path, means providing first and second periodic clock pulses with the second following the first, first and second of the switching means having current paths connected in series between the first clock pulse and a first node, the first capacitance means being provided at the first node, at least part of the second capacitance means being provided between the control means of the first switching means and a second node, the second node being at the intersection in the current paths of the first and second switching means, the control means of the second switching means being connected to the first clock pulse, a third one of the switching means having its current path connected between the first node and the second capacitance means and having its control means connected to the second clock pulse, and a fourth of the switching means having its current path connected between the first node and a data source and having its control means connected to an address signal source.

Claim 21

A self-refreshing memory cell for a random access memory system comprising first and second capacitance means, a plurality of switching means each having a current path and a control means for controlling current through the current path, means providing first and second periodic clock pulses with the second following the first, first and second of the switching means having current paths connected in series between the first clock pulse and a first node, the first capacitance means being provided at the first node, at least part of the second capacitance means being provided between the control means of the first switching means and a second node, the second node being at the intersection in the current paths of the first and second switching means, the control means of the second switching means being connected to the first clock pulse, a third one of the switching means having its current path connected between the first node and the second capacitance means and having its control means connected to the second clock pulse, and a fourth of the switching means having its current path connected between the first node and a data source and having its control means connected to an address signal source.

Claim 22

A memory cell according to claim 18 wherein the switching means are insulated gate field effect transistors.

Claim 23

A memory cell according to claim 19 wherein the first and second clock pulses are non-overlapping.

Claim 24

A memory cell according to claim 20 wherein the third capacitance means exists at the second node.

Claim 25

A memory cell according to claim 21 wherein the voltage on the second capacitance means is caused to bootstrap to a different potential when the first clock pulses switch levels.

Claim 26

A memory cell according to claim 22 wherein the cell reinforces a logic one or logic zero stored on the first and second capacitance means.