US3968480A
Expired / Lapsed
US
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Memory cell
Assignee: Honeywell Inc
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Filing: 1975-03-20
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Granted: 1976-07-06
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Expires: 1995-03-20
Abstract
Abstract A memory system has a data storage element connected by a first memory read device to a first memory output line and by a second memory read device to a second memory output line. A first and a second decoder are connected to the first and second memory read devices, respectively, to read-out data stored in the storage element in response to read address signals applied to the first and second decoders. A "write" operation is effected on the storage element by a write-in device connected between a data input line and the storage element and energized by a third decoder arranged to respond to a write address signal.
Inventors
- 👤 Jeffrey P. Stein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/41; G11C11/412; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
83 words
A memory system comprising: a data storage element, a first output terminal, a first readout means connecting said data storage element to said first output terminal, a second output terminal, a second readout means concurrently connecting said data storage element to said second output terminal, a first decoder means arranged to respond to a memory read operation to energize said first read out means, and, a second decoder arranged to respond to a memory read operation to concurrently energize said second readout means.
Claim 2
Dependent Claim
83 words
A memory system comprising: a data storage element, a first output terminal, a first readout means connecting said data storage element to said first output terminal, a second output terminal, a second readout means concurrently connecting said data storage element to said second output terminal, a first decoder means arranged to respond to a memory read operation to energize said first read out means, and, a second decoder arranged to respond to a memory read operation to concurrently energize said second readout means.
Claim 3
Dependent Claim
18 words
A memory system as set forth in claim 1 wherein said data storage element is a storage capacitor.
Claim 4
Dependent Claim
44 words
A memory system as set forth in claim 1 wherein said data storage element is a flip-flop and said first read-out means is connected to one side of said flip-flop and said second readout means is connected to their other side of said flip-flop.
Claim 5
Dependent Claim
48 words
A memory system as set forth in claim 1 and including a data input terminal, a data write means connecting said data input terminal to said data storage element, and a third decorder means arranged to respond to a memory write operation to energize said data write means.
Claim 6
Dependent Claim
17 words
A memory system as set forth in claim 4 wherein said data storage element is a capacitor.
Claim 7
Dependent Claim
45 words
A memory system as set forth in claim 4 wherein said data storage element is a flip-flop and said data write means is directly connected to one side of said flip-flop and is connected through a logical inverter to the other side of said flip-flop.
Claim 8
Dependent Claim
25 words
A memory system as set forth in claim 1 wherein said data storage element is formed as an integrated circuit element on a semiconductor chip.
Claim 9
Dependent Claim
25 words
A memory system as set forth in claim 2 wherein said data storage element is formed as an integrated circuit element on a semiconductor chip.
Claim 10
Dependent Claim
25 words
A memory system as set forth in claim 4 wherein said data storage element is formed as an integrated circuit element on a semiconductor chip.
Claim 11
Dependent Claim
25 words
A memory system as set forth in claim 5 wherein said data storage element is formed as an integrated circuit element on a semiconductor chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-07-06 | 1980-01-05 | 1980-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-07-06 | 1984-01-05 | 1984-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-07-06 | 1988-01-05 | 1988-07-06 | $7700.00 | Window Closed / Lapsed |