An mos dynamic memory array & refreshing system

Claim 1

In a dynamic memory wherein a plurality of memory cells are simultaneously refreshed, said memory being operative to an enable signal for enabling communications of data with said memory and a refresh signal for controlling the refreshing of said plurality of memory cells, a system for refreshing said plurality of cells wherein said refresh signal and said enable signal are asynchronous comprising: logic circuit means for generating a refresh abort signal in the event said enable signal is applied to said memory while said plurality of cells are being refreshed; and a refresh pulse generator for generating a refresh pulse of a predetermined width for refreshing said plurality of memory cells upon receipt of said refresh signal, said generator including a. means for aborting generation of said refresh pulse upon generation of said refresh abort signal, b. means for generating said refresh pulse after the termination of said refresh abort signal provided said refresh signal is present and said generator has generated a refresh pulse of less than said predetermined width prior to the last generation of said refresh abort signal, and, c. means for preventing generation of said refresh pulse in the event said refresh signal is received by said generator during said communications of data with said memory, whereby said enable signal and refresh signal may be independent.