US3719932A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit organized integrated mnos memory circuit with dynamic decoding and store-restore circuitry
Assignee: Unisys Corp
•
Filing: 1972-04-27
•
Granted: 1973-03-06
•
Expires: 1992-04-27
Abstract
Abstract A digital memory employing a matrix of known variable threshold transistor memory cells arranged in rows and columns. A first address decoder includes a push-pull output which applies an addressed voltage to the gates of transistors in the addressed row of memory cells and a not-addressed voltage to the remaining rows. A second address decoder operates through I/O and storage circuits to permit a single bit of information to be read into or out of the addressed memory cell in a selected column. The memory operates in a five-phase operating cycle. During the first and second phases, appropriate voltages are applied to the gate electrodes of the addressed and non-addressed rows of memory cells and all source and drain lines in the matrix are charged through the I/O and storage circuits. During the third phase, information in each memory cell in the addressed row is read into a temporary storage transistor in the I/O and storage circuits. During the fourth phase, all memory cells in the addressed row are cleared. During the fifth phase, information is re-written into each memory cell from the corresponding temporary storage transistor in the I/O and storage circuits unless new information is to be written into the memory cell selected by the second decoder, in which case the new information is introduced at this time.
Inventors
- 👤 A Cappon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:18
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
254 words
A digital memory employing a matrix of variable threshold transistor memory cells arranged in rows and columns on a common substrate; each of said memory cells containing gate, source and drain electrodes; first decoder means for applying an address voltage to the gate electrodes of all cells in a given row and a non-addressed voltage to the gate electrodes of all remaining cells and to said substrate; said given row being uniquely determined by the value of address input signals received by said decoder means; individual I/O and stoRage circuits for applying drain and source potentials to each column of memory cells; means in each I/O and storage circuit for temporarily storing information read out of an addressed memory cell in the corresponding memory column; second decoder means for supplying a switching signal to a given I/O and storage circuit, said given circuit being uniquely selected by the value of address input signals applied to said decoder from an exterior source; means responsive to said switching signal for providing a single bit of output information corresponding to the information read into the temporary storage circuit selected by said second decoder means; means to apply updated information to said I/O and storage circuit; means responsive to said switching signal for updating the information in the temporary storage means corresponding to the I/O and storage circuit selected by said second decoder; means to clear all memory cells in the selected row; and means to re-write information from said temporary storage means into the corresponding memory cell.
Claim 2
Dependent Claim
254 words
A digital memory employing a matrix of variable threshold transistor memory cells arranged in rows and columns on a common substrate; each of said memory cells containing gate, source and drain electrodes; first decoder means for applying an address voltage to the gate electrodes of all cells in a given row and a non-addressed voltage to the gate electrodes of all remaining cells and to said substrate; said given row being uniquely determined by the value of address input signals received by said decoder means; individual I/O and stoRage circuits for applying drain and source potentials to each column of memory cells; means in each I/O and storage circuit for temporarily storing information read out of an addressed memory cell in the corresponding memory column; second decoder means for supplying a switching signal to a given I/O and storage circuit, said given circuit being uniquely selected by the value of address input signals applied to said decoder from an exterior source; means responsive to said switching signal for providing a single bit of output information corresponding to the information read into the temporary storage circuit selected by said second decoder means; means to apply updated information to said I/O and storage circuit; means responsive to said switching signal for updating the information in the temporary storage means corresponding to the I/O and storage circuit selected by said second decoder; means to clear all memory cells in the selected row; and means to re-write information from said temporary storage means into the corresponding memory cell.
Claim 3
Dependent Claim
254 words
A digital memory employing a matrix of variable threshold transistor memory cells arranged in rows and columns on a common substrate; each of said memory cells containing gate, source and drain electrodes; first decoder means for applying an address voltage to the gate electrodes of all cells in a given row and a non-addressed voltage to the gate electrodes of all remaining cells and to said substrate; said given row being uniquely determined by the value of address input signals received by said decoder means; individual I/O and stoRage circuits for applying drain and source potentials to each column of memory cells; means in each I/O and storage circuit for temporarily storing information read out of an addressed memory cell in the corresponding memory column; second decoder means for supplying a switching signal to a given I/O and storage circuit, said given circuit being uniquely selected by the value of address input signals applied to said decoder from an exterior source; means responsive to said switching signal for providing a single bit of output information corresponding to the information read into the temporary storage circuit selected by said second decoder means; means to apply updated information to said I/O and storage circuit; means responsive to said switching signal for updating the information in the temporary storage means corresponding to the I/O and storage circuit selected by said second decoder; means to clear all memory cells in the selected row; and means to re-write information from said temporary storage means into the corresponding memory cell.
Claim 4
Dependent Claim
254 words
A digital memory employing a matrix of variable threshold transistor memory cells arranged in rows and columns on a common substrate; each of said memory cells containing gate, source and drain electrodes; first decoder means for applying an address voltage to the gate electrodes of all cells in a given row and a non-addressed voltage to the gate electrodes of all remaining cells and to said substrate; said given row being uniquely determined by the value of address input signals received by said decoder means; individual I/O and stoRage circuits for applying drain and source potentials to each column of memory cells; means in each I/O and storage circuit for temporarily storing information read out of an addressed memory cell in the corresponding memory column; second decoder means for supplying a switching signal to a given I/O and storage circuit, said given circuit being uniquely selected by the value of address input signals applied to said decoder from an exterior source; means responsive to said switching signal for providing a single bit of output information corresponding to the information read into the temporary storage circuit selected by said second decoder means; means to apply updated information to said I/O and storage circuit; means responsive to said switching signal for updating the information in the temporary storage means corresponding to the I/O and storage circuit selected by said second decoder; means to clear all memory cells in the selected row; and means to re-write information from said temporary storage means into the corresponding memory cell.
Claim 5
Dependent Claim
49 words
The digital memory of claim 1 wherein said first decoder means includes pairs of buffer transistors for selectively coupling each gate line in the matrix to sources of address and non-address voltages in response to received address input signals whereby all gate lines are maintained at definite predetermined potentials.
Claim 6
Dependent Claim
65 words
The digital memory of claim 2 wherein said second decoder means includes means to apply a switching signal to the I/O and storage circuit corresponding to a selected matrix column and wherein each I/O and storage circuit includes input and output switching transistors through which information can be read into and out of that I/O and storage circuit during the reception of a switching signal.
Claim 7
Dependent Claim
76 words
The digital memory of claim 3 wherein the temporary storage means in each I/O and storage circuit includes a storage transistor, said storage transistor having a gate electrode selectively coupled to the source electrodes of all memory cells in the corresponding matrix column and to the associated input switching transistor so that a bit of information can be applied to the storage transistor gate electrode from a memory cell as well as from an external source.
Claim 8
Dependent Claim
95 words
The digital memory of claim 4 wherein the gate electrode of the storage transistor is coupled to the source electrodes of the memory cells in the associated matrix column through a gating transistor and wherein the drain electrodes of the same memory cells are selectively coupled to ground through a drain line transistor; said source line transistor and said drain line transistor being actuated by a common READ pulse so as to apply a gate voltage to the storage transistor in accordance with information stored in the addressed memory cell in the associated matrix column.
Claim 9
Dependent Claim
168 words
The digital memory of claim 5 wherein the means to re-write information into a memory cell includes means to supply a negative chip enable voltage having a magnitude suitable for writing information into a memory cell to the corresponding I/O and storage circuit; said I/O and storage circuit further including a load transistor connected in series relationship with said storage transistor between said chip enable voltage supply means and ground; said I/O and storage circuit still further including a transmission gating transistor for selectively coupling the junction between said load transistor and said storage transistor to the source electrode of the associated memory cell; said load transistor and said storage transistor being actuated by a common store pulse whereby a voltage of substantially ground potential may be applied to the source electrode of the memory cell when the storage transistor is in a conducting state and a voltage of substantially WRITE potential may be applied to the memory cell when the storage transistor is in a non-conducting state.
References Cited (Backward Citations)
US3387286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-05 | 1976-09-04 | 1977-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-05 | 1980-09-04 | 1981-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-05 | 1984-09-04 | 1985-03-06 | $7700.00 | Window Closed / Lapsed |