Random access memory system utilizing an inverting cell concept

Claim 3

The method of claim 1 wherein the step (c) of logically combining includes the step of performing an exclusive or operation upon said signals to produce an output signal in accordance with the results of said exclusive or operation.

Claim 4

The method of claim 1 wherein binary information signals from said utilization device are written into an addressed one of said cells of said array by performing the steps of: a. logically combining said signal read from one cell of said row of said memory cells associated with the column and a binary information signal from said utilization device to produce an output signal representative of the actual information signal to be written into said addressed cell; b. writing the complement of said output signal in step (a) into said addressed cell; and, c. writing the complement of the signals stored in the remaining cells of said interrogated column back into said column, and said signal stored in said one cell of said row of said memory cells back into said one cell.

Claim 5

The method of claim 3 wherein step (a) of logically combining a signal includes the step of performing an exclusive or operation upon said signals to produce said output signal in accordance with the results of said exclusive or operation.

Claim 8

The method of claim 5 wherein step (a) of logically comparing includes the step of performing an exclusive or operation upon said signals to produce said signal in accordance with the results of said exclusive or operation.

Claim 9

The method of claim 5 wherein binary information signals from said utilization device are written into an addressed one of said cells by performing the steps of: a logically comparing said signal read from said one cell of said row of memory cells with a binary information signal from said utilization device to produce an output signal representative of the actual information signal to be written into said addressed cell; and, b writing the complement of said signal in step (a) into said addressed cell in place of said complement of said signal read from said addressed cell, the signals read from the remaining cells of said interrogated column, and said signal read from said one cell of said row of said memory cells back into said column.

Claim 10

The method of claim 7 wherein said step (a) of logically comparing includes the step of performing an exclusive or operation upon said signals to produce said signal in accordance with the results of said exclusive or operation.

Claim 13

The method of claim 9 wherein the step (c) of logically combining includes the step of performing an exclusive or operation upon the signals applied to the digit/sense line of said addressed memory cell and said common digit/sense line to produce an output signal in accordance with the results of said exclusive or operation.

Claim 14

The method of claim 9 wherein binary information signals from said utilization device are written into an addressed one of said cells by performing the steps of: a logically combining said signal applied to the digit/sense line of said addressed cell and a binary information signal from said utilization device to produce a signal representative of the actual information signal to be written into said addressed cell during said write interval of said cycle; b applying the complement of said signal in step (a) to said digit/sense line in place of said complement of said signal read from said addressed cell for writing into said addressed cell during said write interval of said cycle; and, c applying the signals read from the remaining cells of said interrogated column to corresponding ones of said digit/sense lines and said signal read from said one cell of said row of said memory cells to said common digit/sense line so as to complement the contents of said remaining cells and said one cell during said write interval of said cycle.

Claim 15

The method of claim 11 wherein said step (a) logically combining includes the step of performing an exclusive or operation upon said signals.

Claim 16

A memory system comprising: a plurality of dynamic memory cells, each cell including an input means, ouTput means and charge storage means for storing binary information as an electrical charge; and address selection means coupled to said cells and responsive to input address signals to provide signals for enabling selectively said cells to apply a data signal representative of said binary information stored by said storage means to said output means during a read interval of a memory cycle and to store a data signal applied to said input means during a write interval of said memory cycle; data control means including a plurality of storage devices, each device being connected to a different group of said dynamic memory cells so as to be selectively enabled each time one of said cells within said group is enabled to maintain a count as to the number of times said group has been selected; and, reading means connected to said memory cells and said storage devices, said reading means being operative to logically combine a data signal read out from said output means of an addressed memory cell of a selected group of said cells and a signal read out from said device connected to said group during said read interval of said memory cycle, to produce a signal representative of the actual binary information stored in said cell for transfer to an output device, said group of said cells and said device being enabled by said address selection means during said write interval of said memory cycle to write the data signals read out from said output means of each of said cells of said group and said signal read out from said device during said read interval back into said cells and said device so as to update said count stored by said device and to complement the binary information stored by said charge storage means of said memory cells thereby refreshing said cells contents automatically.

Claim 17

A memory system comprising: a plurality of dynamic memory cells, each cell including an input means, ouTput means and charge storage means for storing binary information as an electrical charge; and address selection means coupled to said cells and responsive to input address signals to provide signals for enabling selectively said cells to apply a data signal representative of said binary information stored by said storage means to said output means during a read interval of a memory cycle and to store a data signal applied to said input means during a write interval of said memory cycle; data control means including a plurality of storage devices, each device being connected to a different group of said dynamic memory cells so as to be selectively enabled each time one of said cells within said group is enabled to maintain a count as to the number of times said group has been selected; and, reading means connected to said memory cells and said storage devices, said reading means being operative to logically combine a data signal read out from said output means of an addressed memory cell of a selected group of said cells and a signal read out from said device connected to said group during said read interval of said memory cycle, to produce a signal representative of the actual binary information stored in said cell for transfer to an output device, said group of said cells and said device being enabled by said address selection means during said write interval of said memory cycle to write the data signals read out from said output means of each of said cells of said group and said signal read out from said device during said read interval back into said cells and said device so as to update said count stored by said device and to complement the binary information stored by said charge storage means of said memory cells thereby refreshing said cells contents automatically.

Claim 18

The combination of claim 13 wherein said reading means includes logic means for performing an exclusive or operation on said signals read from said addressed cell and said device.

Claim 19

The combination of claim 13 in which said dynamic memory cells are arranged in rows and in columns to form a matrix wherein said rows are interconnected along one dimension by an input/output line and a corresponding one of said control devices and said columns corresponding to said groups are interconnected along a second dimension by first and second control lines, said address selection means being operatively connected to said first and second control lines for selectively enabling the memory cells of a column selected in accordance with said input address signals during a memory cycle by applying signals to said first and second control lines defining said read and write intervals.

Claim 20

The combination of claim 13 further including: writing means connected to said control devices and said cells, said writing means including means for receiving an input signal representative of the binary information to be written into a cell designated by said input address signals, said writing means being operative during a write operation to logically combine said signal read out from said device of the column of said designated cell and said input signal to produce an output signal representative of the actual information to be written into said designated cell; and, said address selection means being operative to enable the writing of the complement of said output signal into said designated cell and the writing of the signals read out from the remaining cells of said column and said device during said read interval back into said cells and said device during said write interval.

Claim 21

The combination of claim 16 wherein said writing means includes logic means operative to perform an exclusive or upon said input signal and said signal read out from said device.

Claim 22

The combination of claim 13 wherein each device of said data control means includes a dynamic memory cell similar in construction to said memory cells.

Claim 23

The combination of claim 18 wherein said dynamic memory cell includes: storage, read and write field effect transistors, each transistor having source, control and drain electrodes; said storage transistor being arranged to store digital information by an electrical charge across a node capacitance between said control and source electrodes; said drain electrodes of said read and write transistors being connected in common to an input/output terminal; said read field effect transistor being connected in series with said storage transistor, said read transistor being arranged to sense the state of said storage transistor when conditioned by a signal applied to said control electrode and to apply a signal representative of said state sensed to said input/output terminal; and, said source electrode of said write transistor being connected to said control electrode of said storage transistor, said write transistor being arranged when conditioned by a signal applied to said control electrode to apply a signal representative of the state of said input/output terminal to said storage transistor for storage by said node capacitance.

Claim 24

The combination of claim 19 wherein each of said field effect transistors are insulated gate, P channel enhancement type transistors.

Claim 25

A nondestructive read integrated circuit memory device including a two dimensional array of dynamic memory cells addressed by a plurality of input addressed signals, said cells being interconnected along one dimension by digit/sense lines and said memory cells being interconnected along the other dimension by first and second control lines for applying signals defining read and write intervals of a memory cycle, said device further comprising: data control means including a plurality of storage means, said plurality of storage means being interconnected in said one dimension by a common digit/sense line and each of said storage means being interconnected to said first and second control lines of a different group of memory cells, each of said storage means being arranged to store a reference signal derived independently of the informational content of said different group memory cells used to interpret the informational content of each of the cells within said group; and, read circuit means connected to said common digit/sense line and to said digit/sense lines, said read circuit means including logic means for combining a signal representative of the contents read out from an addressed cell of a group of cells which during said read interval receive a signal on said first control line and a signal read out from said storage means associated therewith, to produce a signal representative of the actual binary information stored by said addressed cell for transfer to an utilization device.

Claim 26

A nondestructive read integrated circuit memory device including a two dimensional array of dynamic memory cells addressed by a plurality of input addressed signals, said cells being interconnected along one dimension by digit/sense lines and said memory cells being interconnected along the other dimension by first and second control lines for applying signals defining read and write intervals of a memory cycle, said device further comprising: data control means including a plurality of storage means, said plurality of storage means being interconnected in said one dimension by a common digit/sense line and each of said storage means being interconnected to said first and second control lines of a different group of memory cells, each of said storage means being arranged to store a reference signal derived independently of the informational content of said different group memory cells used to interpret the informational content of each of the cells within said group; and, read circuit means connected to said common digit/sense line and to said digit/sense lines, said read circuit means including logic means for combining a signal representative of the contents read out from an addressed cell of a group of cells which during said read interval receive a signal on said first control line and a signal read out from said storage means associated therewith, to produce a signal representative of the actual binary information stored by said addressed cell for transfer to an utilization device.

Claim 27

The memory device of claim 21 wherein said group of cells and said storage means in response to a signal on said second control line during said write interval of each read cycle of operation invert the contents of said memory cells of said group and said storage means by applying directly said signals representative of the contents of said cells and said storage means read out during said read interval for writing into said cells of said group thereby automatically refreshing the contents of said cells and modifying said reference signal stored by said storage means for correctly interpreting the informational contents of said cells of said group during a subsequent memory cycle.

Claim 28

The memory device of claim 21 further including: write circuit means connected to said common digit/sense line, said write circuit means including means for receiving a binary information signal from an utilization device representative of information to be written into a designated memory cell and being operative during each write operation to logically combine said signal read out from said storage means during said read interval in response to a signal applied to said first control line and said binary information signal to produce an output signal representatiVe of the actual binary information to be stored in said designated one of said memory cells within said group connected to said storage means; said group of memory cells being responsive to a signal applied to said second control line during said write interval to write the complement of said output signal into said designated one of said memory cells and to write back into the remaining cells and storage means, the signals read out from said remaining cells and said storage means in response to said signal applied to said first control line during said read interval of said same cycle.

Claim 29

The device of claim 21 wherein each of said storage means includes a dynamic memory cell similar in construction to said dynamic cells of said array.

Claim 30

The device of claim 24 wherein said dynamic memory cell includes: storage, read and write field effect transistors, each transistor having source, control and drain electrodes; said storage transistor being arranged to store digital information by an electrical charge across the node capacitance between said control and source electrodes; said drain electrodes of said read and write transistors being connected in common to a digit/sense terminal; said read field effect transistor being connected in series with said storage transistor, said read transistor being arranged to sense the state of said storage transistor when conditioned by a signal applied to said control electrode and to apply a signal representative of said state to said digit/sense terminal; and, said source electrode of said write transistor being connected to said control electrode of said storage transistor, said write transistor being arranged when conditioned by a signal applied to said control electrode to apply a signal representative of the state of said digit/sense terminal to said storage transistor for storage by said node capacitance.

Claim 31

The device of claim 24 wherein said cells of said array are organized into a plurality of sectors.

Claim 32

The device of claim 25 wherein said storage, read and write field effect transistors are insulated gate, P channel enhancement type transistors.

Claim 33

An integrated circuit chip for storing binary information signals transferred from a utilization device and for supplying information signals to said utilization device, said chip comprising: a plurality of dynamic memory cells, each cell including an input means, output means and charge storage means for storing binary information as an electrical charge, said cells being arranged in rows and columns in a matrix defined by a plurality of intersecting digit/sense lines and first and second control lines, each of said cells of a column having said input means connected to the same one of said first control lines and to a different one of said digit/sense lines in common with said output means; address selection means coupled to said digit/sense lines and said first and second control lines and being responsive to input address signals to provide signals thereto for enabling selectively said cells to apply to said digit/sense lines a data signal representative of said binary information stored by said charge storage means from said output means during a read interval of each memory cycle and to store a data signal applied from said digit/sense line to said input means on said charge storage means during a write interval of each said memory cycle; data control means including a plurality of storage devices, each device being connected to a common digit/sense line and to said first and second control lines of a different column of said memory cells so as to be selectively enabled each time said column is selected; read logic means connected to said common digit/sense line and to said plurality of digit/sense lines; and, write logic means being connected to said common digit/sense line and to said plurality of digit/sense lines in common with said read logic means, said write logic means including means for receiVing binary signals from said utilization device; said read logic means being operative to logically combine a data signal read out to one of said plurality of digit/sense lines from said output means of a memory cell of a column of cells selected by said address selection means during a read interval of said memory cycle in response to a signal being applied to said first control line of said column and a signal read out to said common digit/sense line from said storage device of said column during said read interval to produce an output signal representative of the actual binary information stored by said addressed memory cell for transfer to said utilization device; and, said write logic means during each write cycle of operation being operative to logically combine said signal read from said storage device and said binary signals from said utilization device to produce an output signal representative of the actual binary information to be written into said addressed cell in response to a signal applied to said second control line of said column during said write interval of said memory cycle.

Claim 34

An integrated circuit chip for storing binary information signals transferred from a utilization device and for supplying information signals to said utilization device, said chip comprising: a plurality of dynamic memory cells, each cell including an input means, output means and charge storage means for storing binary information as an electrical charge, said cells being arranged in rows and columns in a matrix defined by a plurality of intersecting digit/sense lines and first and second control lines, each of said cells of a column having said input means connected to the same one of said first control lines and to a different one of said digit/sense lines in common with said output means; address selection means coupled to said digit/sense lines and said first and second control lines and being responsive to input address signals to provide signals thereto for enabling selectively said cells to apply to said digit/sense lines a data signal representative of said binary information stored by said charge storage means from said output means during a read interval of each memory cycle and to store a data signal applied from said digit/sense line to said input means on said charge storage means during a write interval of each said memory cycle; data control means including a plurality of storage devices, each device being connected to a common digit/sense line and to said first and second control lines of a different column of said memory cells so as to be selectively enabled each time said column is selected; read logic means connected to said common digit/sense line and to said plurality of digit/sense lines; and, write logic means being connected to said common digit/sense line and to said plurality of digit/sense lines in common with said read logic means, said write logic means including means for receiVing binary signals from said utilization device; said read logic means being operative to logically combine a data signal read out to one of said plurality of digit/sense lines from said output means of a memory cell of a column of cells selected by said address selection means during a read interval of said memory cycle in response to a signal being applied to said first control line of said column and a signal read out to said common digit/sense line from said storage device of said column during said read interval to produce an output signal representative of the actual binary information stored by said addressed memory cell for transfer to said utilization device; and, said write logic means during each write cycle of operation being operative to logically combine said signal read from said storage device and said binary signals from said utilization device to produce an output signal representative of the actual binary information to be written into said addressed cell in response to a signal applied to said second control line of said column during said write interval of said memory cycle.

Claim 35

The circuit chip of claim 28 wherein said read logic means includes means for performing an exclusive or operation upon said data signal and said signal to produce said output signal.

Claim 36

The circuit chip of claim 28 wherein said write logic means includes means for performing a comparison operation upon said signals to produce said output signal.

Claim 37

The circuit chip of claim 28 further including: precharge circuit means connected to said common digit/sense line and to said plurality of digit/sense lines, said precharge circuit means being arranged to charge the capacitance of each of said lines during an interval prior to said read interval; said memory cells of said selected column and said storage device during said read interval being operative to selectively discharge said capacitance of said digit/sense lines in accordance with the state of said charge storage means to apply said data signal to said digit/sense lines representative of said binary information stored by said cells; and, said memory cells of said selected column and said storage device being operative during said write interval of a read cycle to store a charge representative of the state of said digit/sense lines following said read interval whereby the contents of said memory cells are inverted and refreshed and the contents of said storage device are updated at the end of said memory cycle.

Claim 38

The circuit chip of claim 31 wherein each device of said data control means includes a dynamic memory cell similar in construction to said memory cells.

Claim 39

The circuit chip of claim 32 wherein each of said cells includes: storage, read and write field effect transistors, each transistor having source, control and drain electrodes; said storage transistor being arranged to store digital information by an electrical charge across the node capacitance between said control and source electrodes; said drain electrodes of said read and write transistors being connected in common to a digit/sense terminal; said read field effect transistor being connected in series with said storage transistor, said read transistor being arranged to sense the state of said storage transistor when conditioned by a signal applied to said control electrode and to apply a signal representative of said state to said digit/sense terminal; and, said source electrode of said write transistor being connected to said control electrode of said storage transistor, said write transistor being arranged when conditioned by a signal applied to said control electrode to apply a signal representative of the state of said digit/sense terminal to said storage transistor for storage by said node capacitance.

Claim 40

The circuit chip of claim 33 wherein said storage, read and write field effect transistors are insulated gate, P channel enhancement type transistors.

Claim 41

The circuit chip of clAim 28 wherein each of said devices of said data control means includes a memory cell similar in construction to said dynamic memory cells and said chip further includes: precharge circuit means connected to said common digit/sense line and to said plurality of digit/sense lines, said precharge circuit means being arranged to charge the capacitance of each of said lines during an interval prior to said read interval; said memory cells of said selected column and said data control cell being operative to selectively discharge said capacitances of said digit/sense lines in accordance with the state of said charge storage means to apply said data signal to said digit/sense lines representative of said binary information stored by said cells; and, said addressed cell of said selected column being operative during said write interval of a write cycle of operation to store a charge representative of said output signal and the remaining cells of said selected column and said data control cell being operative to store a charge representative of the state of said digit/sense lines following said read interval thereby inverting and refreshing the contents of said remaining cells and said data control cell.

Claim 42

A store comprising: a group of cells, each cell operating in one of two allowable states; an auxiliary cell associated with said group for operating in one of two possible states; means operative during each read cycle of operation for inverting the state of operation of all of the cells of said group and said auxiliary cell; and, means being responsive to the states of any one of said cells and said auxiliary cell for delivering a signal representative of a first type of binary digit when said states are alike and a signal representative of a second type of binary digit when said states are unlike.

Claim 43

A store comprising: a group of cells, each cell operating in one of two allowable states; an auxiliary cell associated with said group for operating in one of two possible states; means operative during each read cycle of operation for inverting the state of operation of all of the cells of said group and said auxiliary cell; and, means being responsive to the states of any one of said cells and said auxiliary cell for delivering a signal representative of a first type of binary digit when said states are alike and a signal representative of a second type of binary digit when said states are unlike.

Claim 44

The store of claim 36 further including: input means for supplying an input signal representative of a binary digit of information to be stored in one of the cells of said group; and, writing means during each write cycle of operation being responsive to said signal and to a signal indicative of the state of said auxiliary cell for conditioning said one cell to operate in one of said states when said auxiliary cell state and said input signal have a first relationship and to operate in the other of said states when said auxiliary cell state and said input signal have a second relationship.

Claim 47

The method of claim 38 wherein the information content of an addressed cell within said array is modified by performing the steps of: a. supplying an input signal representative of a binary digit of the information to be stored in said addressed cell of said group; and, b. conditioning said addressed cell to operate in one state when states of said auxiliary cell and said input signal have a first relationship and to operate in another state when said states have a second relationship.