Self-refreshing random access memory cell

Claim 2

Storage means comprising a first node having capacitance, a second node having capacitance, a third node, an intermittent voltage source, first switching means connecting the voltage source to the third node, second switching means connecting the third node to the first node, the first switching means being controlled by the voltage on the second node, the second switching means being controlled by first recurring clock pulses, a third switching means connecting the first node to the second node, a fourth switching means connecting the third node to a reference potential, the third and fourth switching means being conrolled by second recurring clock pulses out of phase with the first clock pulses.

Claim 3

Storage means according to claim 1 wherein the first node is connected to means for writing in and reading out data.

Claim 4

Storage means according to claim 2 wherein the first node is connected to the means for writing in and reading out data via a fifth switching means which is controlled by an address signal.

Claim 5

Storage means accoding to claim 1 wherein the first and second recurring clock pulses are non-overlapping.

Claim 6

Storage means according to claim 4 wherein a source is provided for the intermittent voltage source which is the same as the first source of recurring clock signals, and said reference potential is provided by said source.

Claim 7

Storage means according to claim 5 wherein the first node is connected to means for writing in and reading out logic levels via a fifth switching means which is controlled by an address signal.

Claim 8

Storage means according to claim 6 wherein the address signal subsists during the first recurring clock signals for reading out and during the second recurring clock signals for writing in.

Claim 9

Storage means according to claim 7 wherein the switching means are insulated gated field effect transistors.

Claim 10

Storage means according to claim 1 wherein the switching means are MOS transistors formed in a monolithic semiconductor device with said nodes.

Claim 11

A memory cell comprising first and second sources of recurring clock signals; first, second and third nodes; a first field effect transistor having a current path connected between a voltage supply and the third node; a second field effect transistor having a current path connected between the third node and the first node, the gate of the second field effect transistor being connected to the first source of clock pulses; a third field effect transistor being connected between the first and second nodes, the gate of the third transistor being connected to the second source of clock signals; a fourth field effect transistor having a current path connected between the third node and the first source of clock signals, the gate of the fourth transistor being connected to the second source of clock signals; and means for reading out and writing in logic levels to the first node.

Claim 12

A memory cell comprising first and second sources of recurring clock signals; first, second and third nodes; a first field effect transistor having a current path connected between a voltage supply and the third node; a second field effect transistor having a current path connected between the third node and the first node, the gate of the second field effect transistor being connected to the first source of clock pulses; a third field effect transistor being connected between the first and second nodes, the gate of the third transistor being connected to the second source of clock signals; a fourth field effect transistor having a current path connected between the third node and the first source of clock signals, the gate of the fourth transistor being connected to the second source of clock signals; and means for reading out and writing in logic levels to the first node.

Claim 13

A memory cell according to claim 10 wherein said voltage supply is the first source of clock signals.

Claim 14

A memory cell according to claim 11 wherein a thin oxide MOS capacitor is provided between the source of said address signals and the first node.

Claim 15

A memory cell according to claim 11 wherein the means for reading out and writing in comprises a fifth field effect transistor having a current path connected between the first node and a source of data.

Claim 16

A memory cell according to claim 13 wherein the gate of the fifth field effect transistor is driven by address signals which are on during the first clock signals for reading out and on during the second clock signals for writing in.

Claim 17

A memory cell according to claim 14 wherein capacitance exists between the second node and the third node.

Claim 18

A memory cell according to claim 15 wherein said capacitance includes a thin oxide MOS capacitor much larger than the gate of the first transistor.

Claim 19

A memory cell according to claim 15 wherein said capacitance is much larger in value than the total of other capacitances existing at said third node.

Claim 20

A self-refreshing memory cell for a random access memory system comprising: a plurality of switching means each having a current path and a control means for controlling current through the current path; means providing sources of first and second periodic clock pulses with the second following the first; first, second and third nodes; first and second of the switching means having current paths connected in series between the source of the first clock pulses and the first node; capacitance means provided between the control means of the first switching means and the third node, the third node being at the intersection in the current paths of the first and second switching means; the control means of the second switching means being connected to the source of the first clock pulses; a third one of the switching means having its current path connected between the first node and the second node and having its control means connected to the source of the second clock pulses; a fourth of the switching means having its current path connected between the third node and the source of the first clock pulses and having its control means connected to the source of the second clock pulses; and a fifth of the switching means having its current path connected between the first node and a data source and having its control means connected to an address signal source.

Claim 21

A self-refreshing memory cell for a random access memory system comprising: a plurality of switching means each having a current path and a control means for controlling current through the current path; means providing sources of first and second periodic clock pulses with the second following the first; first, second and third nodes; first and second of the switching means having current paths connected in series between the source of the first clock pulses and the first node; capacitance means provided between the control means of the first switching means and the third node, the third node being at the intersection in the current paths of the first and second switching means; the control means of the second switching means being connected to the source of the first clock pulses; a third one of the switching means having its current path connected between the first node and the second node and having its control means connected to the source of the second clock pulses; a fourth of the switching means having its current path connected between the third node and the source of the first clock pulses and having its control means connected to the source of the second clock pulses; and a fifth of the switching means having its current path connected between the first node and a data source and having its control means connected to an address signal source.

Claim 22

A memory cell according to claim 18 wherein the switching means are insulated gate field effect transistors and the control means are the gate electrodes of the insulated gate field effect transistors.

Claim 23

A memory cell according to claim 19 wherein the first and second clock pulses are non-overlapping.

Claim 24

A memory cell according to claim 20 wherein a capacitance is provided between the gate of the first switch means and the third node by a thin oxide capacitor which is large compared to the gate of the first switching means.

Claim 25

A memory cell according to claim 21 wherein the cell reinforces a logic one or logic zero stored on the first and second nodes.

Claim 26

A memory cell according to claim 22 wherein a large thin oxide capacitor is provided between the address signal source and the first node, such capacitor being larger than the gate of the fifth switching means.