US8947141B2
Active / In Force
US
⏱️ 7.6 years remaining
Differential amplifiers, clock generator circuits, delay lines and methods
Assignee: Micron Technology Inc
•
Filing: 2014-05-19
•
Granted: 2015-02-03
•
Expires: 2034-05-19
Abstract
Abstract A differential amplifier may be configured to have a duty cycle and/or gain that is adjustable, such as by adjusting the switch points of circuitry in the differential amplifier. The differential amplifier may alternatively or additionally have a hysteresis function by, for example, using a signal feedback from the output of the amplifier to adjust the switch points of circuitry in the differential amplifier. The differential amplifier may be used for a variety of purposes, such as in an input buffer or delay line, either of which may be used, for example, in a clock generator circuit.
Inventors
- 👤 Aaron Willey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:59
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03K; H03K5/00; H03K5/156; H03K5/1565; H03F2203/00; H03F2203/45; H03F2203/45396
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
284 words
A clock generator, comprising: an input buffer configured to receive a clock signal at a signal input node and to output the clock signal at an output node; a delay line including an input node coupled to the output node of the input buffer, an output node, and a duty cycle control node, the delay line being configured to be responsive to a duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of the clock signal being coupled through the delay line, wherein the delay line further comprises a gain control node, and wherein the delay line is configured to have a gain that is adjustable responsive to a signal applied to the gain control node; a phase detector having a first input node coupled to the signal output node of the delay line, a second input node coupled to receive the clock signal applied to the signal input node of the input buffer, and an output node, the phase detector being configured to adjust a delay of delay line based on a phase difference between a signal applied to the first input node and the clock signal applied to the second input node; and a duty cycle control circuit having an input node coupled to the output node of the delay line and an output node coupled to the duty cycle control node of the delay line, the duty cycle control circuit being configured to provide at the output node the duty cycle control signal corresponding to the duty cycle of the clock signal being coupled through the delay line from the input node of the delay line to the output node of the delay line.
Claim 2
Dependent Claim
284 words
A clock generator, comprising: an input buffer configured to receive a clock signal at a signal input node and to output the clock signal at an output node; a delay line including an input node coupled to the output node of the input buffer, an output node, and a duty cycle control node, the delay line being configured to be responsive to a duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of the clock signal being coupled through the delay line, wherein the delay line further comprises a gain control node, and wherein the delay line is configured to have a gain that is adjustable responsive to a signal applied to the gain control node; a phase detector having a first input node coupled to the signal output node of the delay line, a second input node coupled to receive the clock signal applied to the signal input node of the input buffer, and an output node, the phase detector being configured to adjust a delay of delay line based on a phase difference between a signal applied to the first input node and the clock signal applied to the second input node; and a duty cycle control circuit having an input node coupled to the output node of the delay line and an output node coupled to the duty cycle control node of the delay line, the duty cycle control circuit being configured to provide at the output node the duty cycle control signal corresponding to the duty cycle of the clock signal being coupled through the delay line from the input node of the delay line to the output node of the delay line.
Claim 3
Dependent Claim
112 words
The clock generator of claim 1 , wherein the input node of the delay line comprises a first input node and the output node of the delay line comprises a second output node, and wherein the delay line further comprises a second input node coupled to the output node of the input buffer and a second output node, the delay line being configured to be responsive to the duty cycle control signal applied to the duty cycle control node to adjust a duty cycle of a clock signal being coupled through the delay line from the second input node of the delay line to the second output node of the delay line.
Claim 4
Dependent Claim
82 words
The clock generator of claim 2 , wherein the delay line is configured to be responsive to the duty cycle control signal applied to the duty cycle control node of the delay line to adjust a duty cycle of the clock signal coupled from the first signal input node to the first signal output node in inverse proportion to the adjusting of the duty cycle of the clock signal coupled from the second signal input node to the second signal output node.
Claim 5
Dependent Claim
32 words
The clock generator of claim 1 , further comprising a model delay circuit coupled between the output node of the delay line and the input node of the duty cycle control circuit.
Claim 6
Dependent Claim
31 words
The clock generator of claim 4 , wherein the model delay is further coupled between the output node of the delay line and the first input node of the phase detector.
Claim 7
Dependent Claim
55 words
The clock generator of claim 1 , wherein the signal input node of the input buffer comprises a first signal input node, and the signal output node of the input buffer comprises a first signal output node, and wherein the input buffer further comprises a second signal input node and a second signal output node.
Claim 8
Dependent Claim
36 words
The clock generator of claim 1 , wherein the delay line comprises a delay stage that includes a differential amplifier, and wherein the differential amplifier is configured to be responsive to the duty cycle control signal.
Claim 9
Independent Claim
72 words
A method, comprising: coupling a first signal through a delay line; examining a duty cycle of a second signal at an output of the delay line; and before or during coupling the first signal through the delay line: adjusting, based on the examination, the duty cycle of the first signal by adjusting a switch point of a circuit through which the first signal is coupled; and adjusting the gain of the circuit.
Claim 10
Independent Claim
72 words
A method, comprising: coupling a first signal through a delay line; examining a duty cycle of a second signal at an output of the delay line; and before or during coupling the first signal through the delay line: adjusting, based on the examination, the duty cycle of the first signal by adjusting a switch point of a circuit through which the first signal is coupled; and adjusting the gain of the circuit.
Claim 11
Dependent Claim
53 words
The method of claim 8 , further comprising an input buffer through which the signal is coupled prior to being coupled through the delay line, and wherein the act of adjusting the duty cycle of the signal based on the examination comprises adjusting the duty cycle of the signal in the input buffer.
Claim 12
Dependent Claim
33 words
The method of claim 8 , wherein the act of adjusting the duty cycle of the signal based on the examination comprises adjusting the duty cycle of the signal in the delay line.
Claim 13
Dependent Claim
46 words
The method of claim 10 , wherein the delay line comprises an analog delay line having a plurality of analog delay stages, and wherein the act of adjusting the duty cycle of the signal comprises adjusting a switch point of one of the analog delay stages.
Claim 14
Independent Claim
136 words
An apparatus, comprising: a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit and a feedback circuit, wherein the feedback circuit is configured to provide a feedback signal to the differential amplifier circuit, wherein the differential amplifier circuit is configured to adjust the duty cycle of the input signal to provide the output signal based on the feedback signal; and a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
Claim 15
Independent Claim
136 words
An apparatus, comprising: a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit and a feedback circuit, wherein the feedback circuit is configured to provide a feedback signal to the differential amplifier circuit, wherein the differential amplifier circuit is configured to adjust the duty cycle of the input signal to provide the output signal based on the feedback signal; and a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
Claim 16
Dependent Claim
46 words
The apparatus of claim 12 , wherein the feedback circuit comprises an inverter coupled between an output node of the differential amplifier and an input node of the differential amplifier and configured to provide an inverted output signal from the output node to the input node.
Claim 17
Dependent Claim
111 words
The apparatus of claim 12 , wherein the differential amplifier comprises: a first transistor configured to receive the input signal at a first gate; a second transistor configured to receive a second input signal at a second gate, wherein the second input signal is complementary to the input signal received at the first gate; a third transistor configured to receive a control signal from the duty cycle control circuit at a third gate, wherein the adjustment of the duty cycle of the input signal is based on a value of the control signal, wherein the output signal is provided at a node coupled to the second transistor and the third transistor.
Claim 18
Dependent Claim
74 words
The apparatus of claim 14 , wherein the control signal is a first control signal, wherein the differential amplifier further comprises a fourth transistor configured to receive a second control signal at a fourth gate, wherein the second control signal is complementary to the control signal received at the third gate, and wherein the adjustment of the duty cycle of the input signal is further based on a value of the second control signal.
Claim 19
Independent Claim
345 words
An apparatus, comprising: a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit that is configured to adjust the duty cycle of the input signal to provide the output signal, wherein the differential amplifier comprises: a first transistor configured to receive the input signal at a first gate; a second transistor configured to receive a second input signal at a second gate, wherein the second input signal is complementary to the input signal received at the first gate; a third transistor configured to receive a first control signal from the duty cycle control circuit at a third gate, wherein the adjustment of the duty cycle of the input signal is based on a value of the first control signal, wherein the output signal is provided at a node coupled to the second transistor and the third transistor; a fourth transistor configured to receive a second control signal at a fourth gate, wherein the second control signal is complementary to the control signal received at the third gate, and wherein the adjustment of the duty cycle of the input signal is further based on a value of the second control signal; a fifth transistor configured to receive a first feedback signal at a fifth gate, wherein the first feedback signal is based on the output signal; and a sixth transistor configured to receive a second feedback signal at a sixth gate, wherein the second feedback signal is complementary to the first feedback signal, wherein the adjustment of the duty cycle of the input signal is further based on values of the first feedback signal and the second feedback signal; and a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
Claim 20
Independent Claim
345 words
An apparatus, comprising: a delay line configured to receive an input signal and to provide an output signal that is delayed relative to the input signal, the delay line configured to adjust a duty cycle of the input signal to provide the output signal, wherein the delay line comprises a differential amplifier circuit that is configured to adjust the duty cycle of the input signal to provide the output signal, wherein the differential amplifier comprises: a first transistor configured to receive the input signal at a first gate; a second transistor configured to receive a second input signal at a second gate, wherein the second input signal is complementary to the input signal received at the first gate; a third transistor configured to receive a first control signal from the duty cycle control circuit at a third gate, wherein the adjustment of the duty cycle of the input signal is based on a value of the first control signal, wherein the output signal is provided at a node coupled to the second transistor and the third transistor; a fourth transistor configured to receive a second control signal at a fourth gate, wherein the second control signal is complementary to the control signal received at the third gate, and wherein the adjustment of the duty cycle of the input signal is further based on a value of the second control signal; a fifth transistor configured to receive a first feedback signal at a fifth gate, wherein the first feedback signal is based on the output signal; and a sixth transistor configured to receive a second feedback signal at a sixth gate, wherein the second feedback signal is complementary to the first feedback signal, wherein the adjustment of the duty cycle of the input signal is further based on values of the first feedback signal and the second feedback signal; and a duty cycle control circuit configured to control adjustment of the duty cycle of the input signal through the delay line based on a duty cycle of the output signal delayed through a feedback model circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2018-02-02 | 2018-08-04 | 2019-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2022-02-02 | 2022-08-04 | 2023-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2026-02-02 | 2026-08-04 | 2027-02-03 | $7700.00 | Surcharge Window Open |