Differential output driver and semiconductor device having the same

Claim 2

A differential output driver, comprising: a driver including: a differential output portion comprising first and second on-die termination resistors connected to an inverted output signal generation terminal and an output signal generation terminal, respectively to terminate an inverted output signal and an output signal, a first driver connected to the inverted output signal generation terminal to generate the inverted output signal in response to an input signal, and a second driver connected to the output signal generation terminal to generate the output signal in response to an inverted input signal, an inverted output signal drive variable portion connected in parallel to the first driver to vary a driving capability of the first driver in response to a first control signal, and an output signal drive variable portion connected in parallel to the second driver to vary a driving capability of the second driver in response to a second control signal; and a controller for detecting voltage differences between a reference voltage and each of the inverted output signal and the output signal, detecting a voltage difference between the voltage differences to generate an average error value, and generating the first and second control signals in response to the average error value.

Claim 3

The differential output driver according to claim 1 , wherein the controller includes: an average error value generating portion for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the average error value having first and second average error values; and a control portion receiving the first and second average error values to generate the first and second control signals.

Claim 4

The differential output driver according to claim 2 , wherein the average error value generating portion includes: a first average error value calculator for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the first average error value; and a second average error value calculator for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the second average error value having an opposite phase to the first average error value.

Claim 5

The differential output driver according to claim 3 , wherein the first average error value calculator includes: a first differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a first signal; a second differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a second signal; and a third differential amplifier for detecting a voltage difference between the first signal and the second signal and generating the first average error value.

Claim 6

The differential output driver according to claim 3 , wherein the second average error value calculator includes: a fourth differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a third signal; a fifth differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a fourth signal; and a sixth differential amplifier for detecting a voltage difference between the third signal and the fourth signal and generating the second average error value.

Claim 7

The differential output driver according to claim 2 , wherein the first control signal includes first predetermined data bits, and the inverted output signal drive variable portion has a plurality of first NMQS transistors connected in parallel to each other and each data bit of the first predetermined data bits is applied to each of the first NMOS transistors.

Claim 8

The differential output driver according to claim 6 , wherein the second control signal includes second predetermined data bits, and the output signal drive variable portion has a plurality of second NMOS transistors connected in parallel to each other and each data bit of the second predetermined data bits is applied to each of the second NMOS transistors.

Claim 9

The differential output driver according to claim 7 , wherein the control portion includes: a comparator for comparing the first average error value and the second average error value and generating a comparison output signal; a counter for generating fifth and sixth signals in response to the comparison output signal, increasing the number of bits having a “high” level of the fifth signal in response to a first state of the comparison output signal, and decreasing the number of bits having a “high” level of the sixth signal in response to a second state of the comparison output signal, the sixth signal being an inverted signal of the fifth signal; and a control signal generating portion for generating the first control signal in response to the fifth signal and the input signal, and generating the second control signal in response to the sixth signal and the inverted input signal.

Claim 10

The differential output driver according to claim 8 , wherein the control portion further includes: a frequency divider for dividing a clock signal of high frequency to generate a clock signal of low frequency; and an equalization circuit for making the first average error value substantially equal to the second average error value in response to the clock signal of low frequency.

Claim 11

The differential output driver according to claim 9 , wherein the control signal generating portion includes: a first AND circuit for performing an AND operation on the fifth signal and the input signal to generate the first control signal; and a second AND circuit for performing an AND operation on the sixth signal and the inverted input signal to generate the second control signal.

Claim 12

A semiconductor device having a plurality of differential output drivers which generate a plurality of differential output signal pairs, each pair including an inverted output signal and an output signal, each differential output driver comprising: a driver including a differential output portion including first and second on-die termination resistors connected to an inverted output signal generation terminal and an output signal generation terminal, respectively, to terminate the inverted output signal and the output signal, a first driver connected to the inverted output signal generation terminal to generate the inverted output signal in response to an input signal, and a second driver connected to the output signal generation terminal to generate the output signal in response to an inverted input signal, an inverted output signal drive variable portion connected in parallel to the first driver to vary a driving capability of the first driver in response to a first control signal, and an output signal drive variable portion connected in parallel to the second driver to vary a driving capability of the second driver in response to a second control signal, wherein the plurality of differential output drivers include at least one controller for detecting voltage differences between a reference voltage and each of the inverted output signal and the output signal, detecting a voltage difference between the voltage differences to generate an average error value, and generating the first and second control signals in response to the average error value.

Claim 13

A semiconductor device having a plurality of differential output drivers which generate a plurality of differential output signal pairs, each pair including an inverted output signal and an output signal, each differential output driver comprising: a driver including a differential output portion including first and second on-die termination resistors connected to an inverted output signal generation terminal and an output signal generation terminal, respectively, to terminate the inverted output signal and the output signal, a first driver connected to the inverted output signal generation terminal to generate the inverted output signal in response to an input signal, and a second driver connected to the output signal generation terminal to generate the output signal in response to an inverted input signal, an inverted output signal drive variable portion connected in parallel to the first driver to vary a driving capability of the first driver in response to a first control signal, and an output signal drive variable portion connected in parallel to the second driver to vary a driving capability of the second driver in response to a second control signal, wherein the plurality of differential output drivers include at least one controller for detecting voltage differences between a reference voltage and each of the inverted output signal and the output signal, detecting a voltage difference between the voltage differences to generate an average error value, and generating the first and second control signals in response to the average error value.

Claim 14

The semiconductor device according to claim 11 , wherein the controller includes: an average error value generating portion for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the average error value having first and second average error values; and a control portion receiving the first and second average error values to generate the first and second control signals.

Claim 15

The semiconductor device according to claim 12 , wherein the average error value generating portion includes: a first average error value calculator for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the first average error value; and a second average error value calculator for detecting voltage differences between the reference voltage and each of the inverted output signal and the output signal, and detecting a voltage difference between the voltage differences to generate the second average error value of an opposite phase to the first average error value.

Claim 16

The semiconductor device according to claim 13 , wherein the first average error value calculator includes: a first differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a first signal; a second differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a second signal; and a third differential amplifier for detecting a voltage difference between the first signal and the second signal and generating the first average error value.

Claim 17

The semiconductor device according to claim 13 , wherein the second average error value calculator includes: a fourth differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a third signal; a fifth differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a fourth signal; and a sixth differential amplifier for detecting a voltage difference between the third signal and the fourth signal and generating the second average error value.

Claim 18

The semiconductor device according to claim 12 , wherein the first control signal includes first predetermined data bits, and the inverted output signal drive variable portion includes a plurality of first NMOS transistors connected in parallel to each other and each data bit of the first predetermined data bits is applied to each of the first NMOS transistors.

Claim 19

The semiconductor device according to claim 16 , wherein the second control signal includes second predetermined data bits, and the output signal drive variable portion includes a plurality of second NMOS transistors connected in parallel to each other and each data bit of the second predetermined data bits is applied to each of the second NMOS transistors.

Claim 20

The semiconductor device according to claim 17 , wherein the control portion includes: a comparator for comparing the first average error value and the second average error value to generate a comparison output signal; a counter for generating fifth and sixth signals in response to the comparison output signal, increasing the number of bits having a “high” level of the fifth signal in response to a first state of the comparison output signal, and decreasing the number of bits having a “high” level of the sixth signal in response to a second state of the comparison output signal, the sixth signal being an inverted signal of the fifth signal; and a control signal generating portion for generating the first control signal in response to the fifth signal and the input signal, and generating the second control signal in response to the sixth signal and the inverted input signal.

Claim 21

The semiconductor device according to claim 18 , wherein the control portion further includes: a frequency divider for dividing a clock signal of high frequency to generate a clock signal of low frequency; and an equalization circuit for making the first average error value substantially equal to the second average error value in response to the clock signal of low frequency.

Claim 22

The semiconductor device according to claim 19 , wherein the control signal generating portion includes: a first AND circuit for performing an AND operation on the fifth signal and the input signal to generate the first control signal; and a second AND circuit for performing an AND operation on the sixth signal and the inverted input signal to generate the second control signal.

Claim 23

A differential output driver, comprising: a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal; and a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal and a second detected voltage difference between the reference voltage and the inverted output signal.

Claim 24

A differential output driver, comprising: a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control signal; and a controller to generate the first control signal and the second control signal in response to detecting a voltage difference between a first detected voltage difference between a reference voltage and the output signal and a second detected voltage difference between the reference voltage and the inverted output signal.

Claim 25

The differential output driver of claim 21 , wherein the driver further comprises: a first variable driver to drive the inverted output signal in response to the input signal and the first control signal; and a second variable driver to drive the output signal in response to the inverted input signal and the second control signal.

Claim 26

The differential output driver of claim 22 , wherein the controller comprises: an average error value generating unit to generate a first and a second average error value in response to the detected voltage difference between the respective voltage differences between the reference voltage and each of the inverted output signal and output signal; and a control unit to generate the first and second control signal in response to the first and second average error value, respectively.

Claim 27

The differential output driver of claim 23 , wherein the average error value generating unit comprises: a first average error value calculator to generate the first average error value in response to the detected voltage difference between the respective voltage differences between the reference voltage and each of the inverted output signal and the output signal; and a second average error value calculator to generate the second average error value in response to the detected voltage difference between the respective voltage differences between the reference voltage and each of the inverted output signal and the output signal.

Claim 28

The differential output driver according to claim 24 , wherein the first average error value calculator comprises: a first differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a first signal; a second differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a second signal; and a third differential amplifier for detecting a voltage difference between the first signal and the second signal and generating the first average error value.

Claim 29

The differential output driver according to claim 24 , wherein the second average error value calculator includes: a fourth differential amplifier for detecting a voltage difference between the reference voltage and the inverted output signal and generating a third signal; a fifth differential amplifier for detecting a voltage difference between the reference voltage and the output signal and generating a fourth signal; and a sixth differential amplifier for detecting a voltage difference between the third signal and the fourth signal and generating the second average error value.

Claim 30

The differential output driver according to claim 23 , wherein the first variable signal driver includes a plurality of first NMOS transistors connected in parallel to each other and the second variable signal driver includes a plurality of second NMOS transistors connected in parallel to each other.

Claim 31

The output driver according to claim 27 , wherein the first control signal includes a plurality of logic bits applied to the plurality of first NMOS transistors, each logic bit being applied to each of the respective first NMOS transistors, and wherein the second control signal includes a plurality of logic bits applied to the plurality of second NMOS transistors, each logic bit being applied to each of the respective second NMOS transistors.

Claim 32

The differential output driver according to claim 28 , wherein the control unit comprises: a comparator for comparing the first average error value and the second average error value and generating a comparison output signal; a counter for generating fifth and sixth signals in response to the comparison output signal, increasing the number of logic bits having a “high” level of the fifth signal in response to a first state of the comparison output signal, and decreasing the number of logic bits having a “high” level of the sixth signal in response to a second state of the comparison output signal, the sixth signal being an inverted signal of the fifth signal; and a control signal generator for generating the first control signal in response to the fifth signal and the input signal, and generating the second control signal in response to the sixth signal and the inverted input signal.

Claim 33

The differential output driver according to claim 29 , wherein the control unit further includes: a frequency divider for dividing a clock signal of high frequency to generate a clock signal of low frequency; and an equalization circuit for making the first average error value substantially equal to the second average error value in response to the clock signal of low frequency.

Claim 34

The differential output driver according to claim 30 , wherein the control signal generator comprises: a first AND circuit for performing an AND operation on the fifth signal and the input signal to generate the first control signal; and a second AND circuit for performing an AND operation on the sixth signal and the inverted input signal to generate the second control signal.

Claim 37

The method of claim 32 , wherein the first control signal includes a plurality of logic bits and the second control signal includes a plurality of logic bits.

Claim 38

The method of claim 33 , further comprising: generating a first and second avenge error value in response to the third detected voltage difference; and generating the first and second control signal in response to the first and second average error value, respectively.

Claim 39

The method of claim 34 , further comprising: dividing a clock signal of high frequency to generate a clock signal of low frequency; and substantially equalizing the first average error value to the second average error value in response to the clock signal of low frequency.

Claim 40

The method of claim 32 , further comprising: comparing the first average error value with the second average error value; generating a comparison output signal in response to the average error value comparison; generating a first and second signal in response to the comparison output signal, wherein the number of logic bits in the first signal having a “high” level is increased in response to a first state of the comparison output signal, and wherein the number of logic bits in the second signal having a “high” level is decreased in response to a second state of the comparison output signal; and generating the first control signal in response to the first signal and the first input signal and generating the second control signal in response to the second signal and the second input signal.