US7830187B2
Active / In Force
US
⏱️ 2.1 years remaining
Delay locked loop circuit
Assignee: SK Hynix Inc
•
Filing: 2008-12-03
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Granted: 2010-11-09
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Expires: 2028-12-03
Abstract
Abstract A delay locked loop circuit includes a delay locking unit configured to output a first internal clock and a second internal clock, a rising edge of which is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
Inventors
- 👤 Jin-Il Chung
- 👤 Hoon Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:01
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03K; H03K5/00; H03K5/156; H03K5/1565; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; G11C2207/00; G11C2207/22; G11C2207/2227
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
118 words
A delay locked loop circuit, comprising: a delay locking unit configured to output a first internal clock and a second internal clock, wherein a rising edge of the second internal clock is synchronized with that of the first internal clock by delaying a compensated external clock to compensate a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
Claim 2
Dependent Claim
118 words
A delay locked loop circuit, comprising: a delay locking unit configured to output a first internal clock and a second internal clock, wherein a rising edge of the second internal clock is synchronized with that of the first internal clock by delaying a compensated external clock to compensate a skew of a semiconductor memory device; a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks; and a clock control unit configured to control an activation state of the second internal clock after the duty ratio compensation of the external clock.
Claim 3
Dependent Claim
104 words
The delay locked loop circuit of claim 1 , wherein the delay locking unit includes: a first delay locking unit configured to output the first internal clock in response to a result of a first comparison of phase between the compensated external clock and a first feedback clock reflected by a delay modeling of the semiconductor memory device; and a second delay locking unit configured to output the second internal clock by inverting the compensated external clock after delaying the compensated external clock in response to a result of a second comparison of phase between the compensated external clock and a second feedback clock.
Claim 4
Dependent Claim
32 words
The delay locked loop circuit of claim 2 , wherein the duty ratio compensation unit compensates duty ratios of the first and second internal clocks in response to a dual compensation signal.
Claim 5
Dependent Claim
35 words
The delay locked loop circuit of claim 3 , wherein the clock control unit disables toggling of the compensated external clock inputted to the second delay locking unit if the dual compensation signal is deactivated.
Claim 6
Dependent Claim
120 words
The delay locked loop circuit of claim 4 , wherein the duty ratio compensation unit includes: a first compensation unit configured to output the compensated external clock by compensating a duty ratio of the external clock in response to a detection signal and a compensation signal; a second compensation unit configured to mix phases of the first and second internal clocks in response to the compensation signal and the dual compensation signal; a sensing unit configured to generate the detection signal by detecting the duty ratios of the first and second internal clocks; and a compensation control unit configured to generate the compensation signal which enables the first and second compensation units after a locking of the delay locking unit.
Claim 7
Dependent Claim
25 words
The delay locked loop circuit of claim 5 , wherein the compensation control unit enables the locking control unit in response to the detection signal.
Claim 8
Dependent Claim
20 words
The delay locked loop circuit of claim 5 , wherein the first compensation unit drives the external clock if disabled.
Claim 9
Dependent Claim
31 words
The delay locked loop circuit of claim 5 , wherein the first compensation unit generates the compensated external clock regardless of the detection signal after completion of the duty ratio compensation.
Claim 10
Dependent Claim
25 words
The delay locked loop circuit of claim 5 , wherein the second compensation unit drives each of the first and second internal clocks if disabled.
Claim 11
Dependent Claim
113 words
A delay locked loop circuit, comprising: a delay locking unit configured to output a first internal clock and a second internal clock, wherein a rising edge of the second internal clock is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; and a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks, wherein the delay locking unit deactivates the second internal clock after compensating the duty ratio of the external clock.
Claim 12
Dependent Claim
113 words
A delay locked loop circuit, comprising: a delay locking unit configured to output a first internal clock and a second internal clock, wherein a rising edge of the second internal clock is synchronized with that of the first internal clock by delaying a compensated external clock for compensating a skew of a semiconductor memory device; and a duty ratio compensation unit configured to generate the compensated external clock by compensating a duty ratio of an external clock of the semiconductor memory device and to compensate duty ratios of the first and second internal clocks, wherein the delay locking unit deactivates the second internal clock after compensating the duty ratio of the external clock.
Claim 13
Dependent Claim
132 words
The delay locked loop circuit of claim 10 , wherein the delay locking unit includes: a first delay locking unit configured to output the first internal clock in response to a result of a comparison of phase as between the compensated external clock and a first feedback clock reflected by a delay modeling of the semiconductor memory device; a second delay locking unit configured to output the second internal clock by inverting the compensated external clock after delaying the compensated external clock in response to a result of a comparison of phase between the compensated external clock and a second feedback clock; and a clock control unit configured to disable toggling of the compensated external clock inputted to the second delay locking unit after compensating the duty ratio of the external clock.
Claim 14
Dependent Claim
116 words
The delay locked loop circuit of claim 10 , wherein the duty ratio compensation unit includes: a first compensation unit configured to output the compensated external clock by compensating a duty ratio of the external clock in response to a detection signal and a compensation signal; a second compensation unit configured to mix phases of the first and second internal clocks in response to the compensation signal and the dual compensation signal; a sensing unit configured to generate the detection signal by detecting duty ratios of the first and second internal clocks; and a compensation control unit configured to generate the compensation signal which enables the compensation unit after a locking of the delay locking unit.
Claim 15
Dependent Claim
23 words
The delay locked loop circuit of claim 12 , wherein the clock control unit is enabled if the dual compensation signal is deactivated.
References Cited (Backward Citations)
US6452432B2
Cited
KR20030090129A
Cited
US6956418B2
Cited
US20050024107A1
Cited
KR20060000866A
Cited
US7282974B2
Cited
US20070069781A1
Cited
US7449930B2
Cited
KR20070036641A
Cited
US20070069775A1
Cited
US20070069776A1
Cited
US7358784B2
Cited
US7388415B2
Cited
US20070188206A1
Cited
US7489171B2
Cited
KR20080001124A
Cited
US20080136476A1
Cited
US7633323B2
Cited
US20080169853A1
Cited
US7567103B2
Cited
US7598783B2
Cited
US20100052745A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2013-11-08 | 2014-05-10 | 2014-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2017-11-08 | 2018-05-10 | 2018-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2021-11-08 | 2022-05-10 | 2022-11-09 | $7700.00 | Window Closed / Lapsed |