Delay locked loop

Claim 2

A delay locked loop device, comprising: a delay locked loop including a duty cycle compensator for receiving first and second clocks; and a reset control means for resetting the delay locked loop if a phase difference between the first and second clocks is greater than a predetermined amount after the delay locked loop achieves a delay locking state.

Claim 3

The delay locked loop device as recited in claim 1 , wherein the reset control means includes: a phase difference detecting block for detecting the phase difference between the first and second clocks; a reset signal generating block for generating a reset signal in response to an enable signal for the duty cycle compensator and an output from the phase difference detecting block; and a reset pulse generating block for generating a reset pulse signal based on the reset signal.

Claim 4

The delay locked loop device as recited in claim 2 , wherein the predetermined amount is larger than an operational jitter of the delay locked loop.

Claim 5

The delay locked loop device as recited in claim 2 , wherein the phase difference detecting block includes: a first delay block for delaying the second clock by the predetermined amount which is larger than an operational jitter of the delay locked loop; a second delay block for delaying the first clock by the predetermined amount; a first phase detector for generating a first phase detect signal in response to the first clock and an output of the first delay block; and a second phase detector for generating a second phase detect signal in response to the second clock and an output of the second delay block.

Claim 6

The delay locked loop device as recited in claim 4 , wherein the reset signal generating block includes: a detection input block for performing a predetermined logic operation to outputs of the phase difference detecting block; a switching block for transferring the enable signal for the duty cycle compensator in response to an output of the detection input block; and a latch block for latching an output of the switching block to generate the reset signal.

Claim 7

The delay locked loop device as recited in claim 5 , wherein the detection input block includes: a first inverter for inverting an output of the first phase detector; a second inverter for inverting an output of the second phase detector; and a logic NAND gate for performing a logic NAND operation to outputs of the first and second inverters.

Claim 8

The delay locked loop device as recited in claim 5 , wherein the switching block includes: a third inverter for inverting the enable signal for the duty cycle compensator; a PMOS transistor for supplying a power voltage in response to an output of the third inverter; a first NMOS transistor for supplying a ground voltage in response to the output of the third inverter; and a second NMOS transistor for transferring an output of the first NMOS transistor in response to the output of the detection input block, wherein a predetermined voltage supplied between the PMOS transistor and the second NMOS transistor is output as the output of the switching block.

Claim 9

The delay locked loop device as recited in claim 5 , wherein the latching block includes: an inverter latch for latching the output of the switching block; and a fourth inverter for inverting an output of the inverter latch to generate the reset signal.

Claim 10

The delay locked loop device as recited in claim 4 , wherein the reset pulse generating block includes: a first inverting group containing an odd number of serially connected inverters; and a logic NOR gate for receiving the reset signal and an output of the first inverting group to form the reset pulse signal.

Claim 11

The delay locked loop device as recited in claim 1 , wherein the delay locked loop includes: a first delay block for generate the first clock; and a second delay block for generate the second clock, wherein the reset control means controls the first and second delay blocks to thereby reset the delay locked loop.

Claim 12

The delay locked loop device as recited in claim 2 , wherein the delay locked loop includes: a first delay block for generate the first clock; and a second delay block for generate the second clock, wherein the reset pulse signal resets the first and second delay blocks.

Claim 13

The delay locked loop device as recited in claim 1 , wherein the delay locked loop includes: a clock buffer for buffering an external clock to generate first and second internal clocks and a reference clock; a first delay block for delaying the first internal clock by a controlled delay amount to generate the first clock; a second delay block for delaying the second internal clock by a controlled delay amount to generate the second clock; a DCC mixer for mixing phases of the first and second clocks; a dummy DCC mixer for mixing the phases of the first and second clocks; a DCC phase comparator for comparing the phases of the first and second clocks; a mixer controller for controlling the DCC mixer and the dummy DCC mixer based on a comparison result of the DCC phase comparator; a first delay replica model for feeding back an output of the DCC mixer to generate a first feedback clock; a first phase comparator for comparing a phase of the first feedback clock with that of the reference clock to control the first delay block; a second delay replica model for feeding back an output of the dummy DCC mixer to generate a second feedback clock; and a second phase comparator for comparing a phase of the second feedback clock with that of the reference clock to control the second delay block.

Claim 14

A semiconductor memory device, comprising: a delay locked loop for delaying an external clock, adjusting a duty cycle ratio of delayed clocks, and generating DLL output clocks to thereby synchronize a timing of outputting data responsive to a read command with the external clock; and a reset control means for comparing phase of the delayed clocks to reset the delay locked loop after a delay locking state.

Claim 15

A semiconductor memory device, comprising: a delay locked loop for delaying an external clock, adjusting a duty cycle ratio of delayed clocks, and generating DLL output clocks to thereby synchronize a timing of outputting data responsive to a read command with the external clock; and a reset control means for comparing phase of the delayed clocks to reset the delay locked loop after a delay locking state.

Claim 16

The semiconductor memory device as recited in claim 13 , wherein the reset control means includes: a phase difference detecting block for detecting a phase difference between the delayed clocks; a reset signal generating block for generating a reset signal in response to an enable signal for duty cycle compensating block and an output from the phase difference detecting block; and a reset pulse generating block for generating a reset pulse signal based on the reset signal.

Claim 17

The semiconductor memory device as recited in claim 14 , wherein the predetermined amount is larger than an operational jitter of the delay locked loop.

Claim 18

The semiconductor memory device as recited in claim 14 , wherein the phase difference detecting block includes: a first delay block for delaying the second clock by the predetermined amount which is larger than an operational jitter of the delay locked loop; a second delay block for delaying the first clock by the predetermined amount; a first phase detector for generating a first phase detect signal in response to the first clock and an output of the first delay block; and a second phase detector for generating a second phase detect signal in response to the second clock and an output of the second delay block.

Claim 19

The semiconductor memory device as recited in claim 14 , wherein the reset signal generating block includes: a detection input block for performing a predetermined logic operation to outputs of the phase difference detecting block; a switching block for transferring the enable signal for the duty cycle compensator in response to an output of the detection input block; and a latch block for latching an output of the switching block to generate the reset signal.

Claim 20

The semiconductor memory device as recited in claim 13 , wherein the delay locked loop includes: a delay locking block for controlling a delay amount of the external clock to generate the delayed clocks; and a duty cycle compensating block for adjusting a duty cycle ratio of the delayed clocks.

Claim 21

The delay locked loop device as recited in claim 18 , wherein duty cycle compensating block includes: a DCC mixer for mixing phases of the first and second clocks; a dummy DCC mixer for mixing the phases of the first and second clocks; a DCC phase comparator for comparing the phases of the first and second clocks; and a mixer controller for controlling the DCC mixer and the dummy DCC mixer based on a comparison result of the DCC phase comparator.

Claim 22

The delay locked loop device as recited in claim 18 , wherein the delay locking block includes: a clock buffer for buffering an external clock to generate first and second internal clocks and a reference clock; a first delay block for delaying the first internal clock by a controlled delay amount to generate the first clock; a second delay block for delaying the second internal clock by a controlled delay amount to generate the second clock; a first delay replica model for feeding back an output of the duty cycle compensating block to generate a first feedback clock; a first phase comparator for comparing a phase of the first feedback clock with that of the reference clock to control the first delay block; a second delay replica model for feeding back the output of the duty cycle compensating block to generate a second feedback clock; and a second phase comparator for comparing a phase of the second feedback clock with that of the reference clock to control the second delay block.