US6281728B1
Expired / Lapsed
US
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Delay locked loop circuit
Assignee: SK Hynix Inc
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Filing: 2000-04-07
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Granted: 2001-08-28
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Expires: 2020-04-07
Abstract
Abstract A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal; first oscillation means for generating a first pulse signal; second oscillation means for generating a second pulse signal; phase detection means for receiving the external clock signal and an internal clock signal and generating a phase detection signal; second delay means for delaying the delay clock signal by one period of the first pulse signal of the first oscillation means to generate a first plurality of clock signals; third delay means for delaying the delay clock signal by one period of the second pulse signal of the second oscillation means to generate a second plurality of clock signals; selection means for selecting a pair of clock signals having the same delay time from the first plurality of clock signals and the second plurality of clock signals; logic means for combining the pair of clock signals selected from the selection means to generate the internal clock signal; and control means for generating control signals for controlling the first delay means, the first and second oscillation means and the selection means and a reset signal for resetting the first and second delay means in accordance with the phase detection signal from the detection means.
Inventors
- 👤 Jun Bae Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:55
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H03L7/081
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
361 words
A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal delayed for a selected time; first oscillation means for generating a first pulse signal having a constant period in the first logic level interval of the delay clock signal from the first delay means; second oscillation means for generating a second pulse signal having the same period as the first pulse signal in the second logic level interval of the delay clock signal from the first delay means; phase detection means for receiving the external clock signal and an internal clock signal and generating a phase detection signal between two clock signals; second delay means for successively delaying the delay clock signal by one period of the first pulse signal of the first oscillation means to generate a first plurality of clock signals in the first logic level interval of the delay clock signal, each of the first plurality of clock signals having two times period of the delay clock signal; third delay means for successively delaying the delay clock signal by one period of the second pulse signal of the second oscillation means to generate a second plurality of clock signals in the second level interval of the delay clock signal, each of the second plurality of clock signals having two times period of the delay clock signal; selection means for selecting a pair of clock signals having the same delay time from the first plurality of clock signals and the second plurality of clock signals; logic means for combining the pair of clock signals selected from the selection means to generate the internal clock signal, the internal clock signal having the same period of the external clock signal and the internal clock signal being a delayed clock signal of the external clock signal by a selected period of the first pulse signal; and control means for generating control signals for controlling the first delay means, the first and second oscillation means and the selection means and a reset signal for resetting the first and second delay means in accordance with the phase detection signal from the detection means.
Claim 2
Dependent Claim
361 words
A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal delayed for a selected time; first oscillation means for generating a first pulse signal having a constant period in the first logic level interval of the delay clock signal from the first delay means; second oscillation means for generating a second pulse signal having the same period as the first pulse signal in the second logic level interval of the delay clock signal from the first delay means; phase detection means for receiving the external clock signal and an internal clock signal and generating a phase detection signal between two clock signals; second delay means for successively delaying the delay clock signal by one period of the first pulse signal of the first oscillation means to generate a first plurality of clock signals in the first logic level interval of the delay clock signal, each of the first plurality of clock signals having two times period of the delay clock signal; third delay means for successively delaying the delay clock signal by one period of the second pulse signal of the second oscillation means to generate a second plurality of clock signals in the second level interval of the delay clock signal, each of the second plurality of clock signals having two times period of the delay clock signal; selection means for selecting a pair of clock signals having the same delay time from the first plurality of clock signals and the second plurality of clock signals; logic means for combining the pair of clock signals selected from the selection means to generate the internal clock signal, the internal clock signal having the same period of the external clock signal and the internal clock signal being a delayed clock signal of the external clock signal by a selected period of the first pulse signal; and control means for generating control signals for controlling the first delay means, the first and second oscillation means and the selection means and a reset signal for resetting the first and second delay means in accordance with the phase detection signal from the detection means.
Claim 3
Dependent Claim
43 words
The delay locked loop circuit as claimed in claim 1 , wherein the first logic level interval is logic high level interval of the delay clock signal and the second logic level interval is logic low level interval of the delay clock signal.
Claim 4
Dependent Claim
140 words
The delay locked loop circuit as claimed in claim 1 , wherein the second delay means includes: D-flip flops being activated for a first logic level interval of the delay clock signal from the first delay means and for generating clock signals in the first logic level interval of the delay clock signal from the first delay means which successively delayed by one period of the first pulse signal from the first oscillation means from the first logic level of the delay clock signal from the first delay means; and T-flip flops reset by the reset signal from the control means and for generating the first plurality of clock signals which have two times period of the clock signals from the D-flip flops and are successively delayed by one period of the first pulse signal from the first oscillation means.
Claim 5
Dependent Claim
141 words
The delay locked loop circuit as claimed in claim 1 , wherein the third delay means includes: D-flip flops D-FF being activated for the second logic level interval of the delay clock signal from the first delay means and for generating clock signals in the second logic level interval of the delay clock signal from the first delay means which successively delayed by one period of the second pulse signal from the second oscillation means from the second logic level of the delay clock signal from the first delay means; and T-flip flops reset by the reset signal from the control means and for generating the second plurality of clock signals which have two times period of the clock signals from the D-flip flops and are successively delayed by one period of the second pulse signal from the second oscillation means.
Claim 6
Dependent Claim
20 words
The delay locked loop circuit as claimed in claim 1 , wherein the selection means is comprised of a multiplexer.
Claim 7
Dependent Claim
22 words
The delay locked loop circuit as claimed in claim 1 , wherein the logic means is comprised of an exclusive OR gate.
Claim 8
Dependent Claim
24 words
The delay locked loop circuit as claimed in claim 1 , wherein the first and second oscillation means are comprised of voltage controlled oscillators.
References Cited (Backward Citations)
US5990714A
Cited
US6198690B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |