DLL driving circuit for use in semiconductor memory device

Claim 2

A DLL driving circuit for use in a semiconductor memory device, the DLL driving circuit comprising: a DLL reset signal generation means for receiving a first bank selection address, a first address and a mode register set signal in order to generate a DLL reset signal; a disable-DLL signal generation means for receiving a second bank selection address and the mode register set signal in order to generate a disable-DLL signal; and a reset driving means for receiving the disable-DLL signal outputted from the disable-DLL signal generation means and driving the DLL reset signal generation means.

Claim 3

The DLL driving circuit recited in claim 1 , wherein the DLL reset signal generation means includes: a first input unit for receiving the first bank selection address, the first address outputted from an address buffer and the mode register set signal; a second input unit for receiving an output signal of the first input unit and an output signal of the reset driving means; a pulse generation means for receiving an output signal of the second input unit and generating a pulse signal; and an output means for amplifying and outputting an output signal of the pulse generation unit.

Claim 4

The DLL driving circuit as recited in claim 2 , wherein the disable-DLL signal generation means receives at least the second bank selection address determined by a combination of bank addresses, the mode register set signal outputted from a command decoder, and a second address outputted from an address buffer and generates the disable-DLL signal.

Claim 5

The DLL driving circuit as recited in claim 3 , wherein the disable-DLL signal generation means includes: an RGWT signal generation unit for receiving the second bank selection address and the mode register set signal; and a disable-DLL signal generation unit for receiving an output signal of the RGWT signal generation unit and the second address.

Claim 6

The DLL driving circuit as recited in claim 4 , wherein the RGWT signal generation unit includes: an inverter chain for receiving the mode register set signal; a pulse generation unit for receiving the second bank selection address and an output signal of the inverter chain and generating a pulse signal; and an output unit for amplifying and outputting an output signal of the pulse generation unit.

Claim 7

The DLL driving circuit as recited in claim 5 , wherein the disable-DLL signal generation means includes: a first transmission gate formed on a path through which the second address is inputted and controlled by the RGWT signal outputted from the RGWT signal generation unit; a first latch unit formed on an output node of the first transmission gate; a second transmission gate formed on a data output path of the first latch unit and controlled by the RGWT signal; a second latch unit formed on an output node of the second transmission gate; a reset transistor for resetting the output node of the second transmission gate in response to a power up signal; and an output unit having two inverters connected in series, for amplifying and outputting an output data of the second latch unit.

Claim 8

The DLL driving circuit as recited in claim 1 , wherein the reset driving means includes an EMRS_RESETZ signal generation unit for receiving the disable-DLL signal outputted from the disable-DLL signal generation means in order to generate an EMRS_RESETZ signal for driving the DLL reset signal generation means.

Claim 9

The DLL driving circuit as recited in claim 7 , wherein the reset driving means further includes a disable-fuse unit for the EMRS_RESETZ signal generation unit to output the EMRS_RESETZ signal, in response to disable-fuse signal outputted from the disable-fuse unit.

Claim 10

The DLL driving circuit as recited in claim 8 , wherein the disable-fuse unit includes: a fuse connected between a power supply voltage and an output node; a transistor acting as a resistor, the transistor being connected between the output node and the power supply voltage and having a gate connected to the power supply voltage; and an output node for outputting the disable-fuse signal.

Claim 11

The DLL driving circuit as recited in claim 8 , wherein the driving means includes: an input unit for receiving the disable-DLL signal; a delay unit for delaying an output signal of the input unit; a pulse generation unit for receiving an output signal of the delay unit and generating a pulse signal; and an output unit for outputting the pulse signal in response to an output signal of the disable-fuse unit.

Claim 12

The DLL driving circuit as recited in claim 10 , wherein the disable-fuse unit includes: a fuse connected between a power supply voltage and an output node; a transistor acting as a resistor, the transistor being connected between the output node and the power supply voltage and having a gate connected to the power supply voltage; and an output node for outputting the disable-fuse signal.

Claim 15

The method as recited in claim 12 , wherein the DLL reset signal is outputted from a DLL reset signal generation means, the DLL reset signal generation means including: a first input unit for receiving the first bank selection address, a first address outputted from an address buffer and the mode register set signal; a second input unit for receiving an output signal of the first input unit and an output signal of the reset driving means; a pulse generation means for receiving an output signal of the second input unit and generating a pulse signal; and an output means for amplifying and outputting an output signal of the pulse generation unit.

Claim 16

The method as recited in claim 13 , wherein the disable-DLL signal is generated in response to a second bank selection address determined by a combination of bank addresses, the mode register set signal outputted from a command decoder, and a second address outputted from an address buffer.

Claim 17

The method as recited in claim 14 , wherein the disable-DLL signal is outputted from a disable-DLL signal generation means, the disable-DLL signal generation means including: an RGWT signal generation unit for receiving the second bank selection address and the mode register set signal; and a disable-DLL signal generation unit for receiving an output signal of the RGWT signal generation unit and the second address.

Claim 18

The method as recited in claim 12 , wherein the step c) is carried out by a reset driving means for receiving the disable-DLL signal and outputting the DLL reset signal.

Claim 19

The method as recited in claim 16 wherein the reset driving means further includes a disable-fuse unit, the reset driving means outputting the DLL reset signal in response to an output signal of the disable-fuse unit.

Claim 20

A semiconductor memory, device having a DLL, comprising: a DLL reset signal generation means for receiving a first bank selection address, a first address and a mode register set signal in order to generate a DLL reset signal for resetting the DLL; an RGWT signal generation means for receiving a second bank selection address and the mode register set signal; and a disable-DLL signal generation means for receiving an output signal of the RGWT signal generation means and a second address in order to generate a disable-DLL signal; a reset driving means for receiving the disable-DLL signal in order to generate an EMRS 13 RESETZ signal for driving the DLL reset signal generation means, wherein the resetting of the DLL is driven through the reset driving means if the mode register set signal for resetting the DLL is not inputted.

Claim 21

A semiconductor memory, device having a DLL, comprising: a DLL reset signal generation means for receiving a first bank selection address, a first address and a mode register set signal in order to generate a DLL reset signal for resetting the DLL; an RGWT signal generation means for receiving a second bank selection address and the mode register set signal; and a disable-DLL signal generation means for receiving an output signal of the RGWT signal generation means and a second address in order to generate a disable-DLL signal; a reset driving means for receiving the disable-DLL signal in order to generate an EMRS 13 RESETZ signal for driving the DLL reset signal generation means, wherein the resetting of the DLL is driven through the reset driving means if the mode register set signal for resetting the DLL is not inputted.

Claim 22

The semiconductor memory device as recited in claim 18 , wherein the reset driving means further includes a disable-fuse unit for the reset driving means to output the EMRS_RESETZ signal, in response to an output signal of the disable-fuse unit.