Power reduction for delay locked loop circuits

Claim 2

A delay locked loop comprising: an input node for receiving a clock signal; a delay line including a plurality of entry-point gates for receiving the clock signal to generate a delayed signal at an output node; a phase detector for produce shifting signals based on the clock signal and the delayed signal; and a shift register including a plurality of register cells for receiving the shifting signals to select one of the entry-point gates to be an active entry-point gate for allowing the clock signal to enter the active entry-point gate and propagate to the output node, wherein the active entry-point gate connects to multiple register cells of the plurality of register cells, the multiple register cells having different logic values.

Claim 3

The delay locked loop of claim 1 , wherein the delay line further includes a plurality of propagation gates for propagating the clock signal from the active entry-point to the output node, wherein each of the entry point-gates connects to multiple propagation gates of the plurality of propagation gates and multiple register cells.

Claim 4

The delay locked loop of claim 1 , wherein each of the entry-point gates is a NAND gate.

Claim 5

The delay locked loop of claim 1 , wherein each of the entry-point gates is a three-input NAND gate.

Claim 6

The delay locked loop of claim 2 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 7

The delay locked loop of claim 2 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 8

A delay locked loop comprising: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at and an entry point at one of the delay cells; a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells includes an entry point gate connected to multiple register cells of the plurality of register cells.

Claim 9

A delay locked loop comprising: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at and an entry point at one of the delay cells; a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells includes an entry point gate connected to multiple register cells of the plurality of register cells.

Claim 10

A delay locked loop comprising: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at and an entry point at one of the delay cells; a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells connects to multiple register cells of the plurality of register cells, wherein each of the delay cells includes: a plurality of propagation gates for propagating the clock signal after the clock signal enters the entry point; and an entry-point gate connected to the input node and to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 11

A delay locked loop comprising: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at and an entry point at one of the delay cells; a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells connects to multiple register cells of the plurality of register cells, wherein each of the delay cells includes: a plurality of propagation gates for propagating the clock signal after the clock signal enters the entry point; and an entry-point gate connected to the input node and to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 12

The delay locked loop of claim 8 , wherein the entry-point gate is a NAND gate.

Claim 13

The delay locked loop of claim 8 , wherein the entry-point gate is a three-input NAND gate.

Claim 14

The delay locked loop of claim 8 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 15

The delay locked loop of claim 8 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 16

A delay locked loop comprising: an input node for receiving a clock signal and output node for providing a delayed signal; a delay line for applying a delay to the external clock signal to generate a delayed signal at an output node, each of the delay cells including: an entry-point gate connected to the input node for selectively allowing the entry of the clock signal into the delay line; and a plurality of propagation gates connected to the entry-point gate for propagating the clock signal from the entry-point gate to the output node; and a phase detector for producing shifting signals based on the clock signal and the delayed signal; and a shift register including a plurality of register cells, each of the delay cells connects to multiple register cells of the plurality of register cells and multiple propagation gates of the plurality of propagation gates for allowing adjacent register cells having unequal logic values to adjust the delay applied to the external signal based on the shifting signals.

Claim 17

A delay locked loop comprising: an input node for receiving a clock signal and output node for providing a delayed signal; a delay line for applying a delay to the external clock signal to generate a delayed signal at an output node, each of the delay cells including: an entry-point gate connected to the input node for selectively allowing the entry of the clock signal into the delay line; and a plurality of propagation gates connected to the entry-point gate for propagating the clock signal from the entry-point gate to the output node; and a phase detector for producing shifting signals based on the clock signal and the delayed signal; and a shift register including a plurality of register cells, each of the delay cells connects to multiple register cells of the plurality of register cells and multiple propagation gates of the plurality of propagation gates for allowing adjacent register cells having unequal logic values to adjust the delay applied to the external signal based on the shifting signals.

Claim 18

The delay locked loop of claim 13 , wherein each of the entry-point gates is a NAND gate.

Claim 19

The delay locked loop of claim 13 , wherein each of the entry-point gates is a three-input NAND gate.

Claim 20

The delay locked loop of claim 13 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 21

The delay locked loop of claim 13 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 22

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of entry-point gates for receiving the clock signal to generate a delayed signal at an output node; a phase detector for produce shifting signals based on the clock signal and the delayed signal; and a shift register including a plurality of register cells for receiving the shifting signals to select one of the entry-point gates to be an active entry-point gate for allowing the clock signal to enter the active entry-point gate and propagate to the output node, wherein the active entry-point gate connects to multiple register cells of the plurality of register cells having different logic values.

Claim 23

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of entry-point gates for receiving the clock signal to generate a delayed signal at an output node; a phase detector for produce shifting signals based on the clock signal and the delayed signal; and a shift register including a plurality of register cells for receiving the shifting signals to select one of the entry-point gates to be an active entry-point gate for allowing the clock signal to enter the active entry-point gate and propagate to the output node, wherein the active entry-point gate connects to multiple register cells of the plurality of register cells having different logic values.

Claim 24

The memory device of claim 18 , wherein the delay line further includes a plurality of propagation gates for propagating the clock signal from the active entry-point to the output node, wherein each of the entry point-gates connects to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 25

The memory device of claim 18 , wherein each of the entry-point gates is a NAND gate.

Claim 26

The memory device of claim 18 , wherein each of the entry-point gates is a three-input NAND gate.

Claim 27

The memory device of claim 18 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 28

The memory device of claim 19 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 29

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at an entry point at one of the delay cells; and a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells includes an entry point gate connected to multiple register cells of the plurality of register cells.

Claim 30

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at an entry point at one of the delay cells; and a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells includes an entry point gate connected to multiple register cells of the plurality of register cells.

Claim 31

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at an entry point at one of the delay cells; and a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells connects to multiple register cells of the plurality of register cells, wherein each of the delay cells includes: a plurality of propagation gates for propagating the clock signal after the clock signal enters the entry point; and an entry-point gate connected to the input node and to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 32

A memory device comprising: a main memory; an output circuit; and a delay locked loop connected between the main memory and the output circuit for, the delay locked loop including: an input node for receiving a clock signal; a delay line including a plurality of delay cells for generating a delayed signal based on the clock signal entered the delay line at an entry point at one of the delay cells; and a phase detector for producing shifting signals based the clock signal and the delayed signal; and a shift register having a plurality of register cells for shifting the entry point based on the shifting signals to adjust signal timing of the delayed signal, wherein each of the delay cells connects to multiple register cells of the plurality of register cells, wherein each of the delay cells includes: a plurality of propagation gates for propagating the clock signal after the clock signal enters the entry point; and an entry-point gate connected to the input node and to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 33

The memory device of claim 25 , wherein the entry-point gate is a NAND gate.

Claim 34

The memory device of claim 25 , wherein the entry-point gate is a three-input NAND gate.

Claim 35

The memory device of claim 25 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 36

The memory device of claim 25 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 39

The system of claim 30 , wherein the delay line further includes a plurality of propagation gates for propagating the clock signal from the active entry-point to the output node, wherein each of the entry point-gates connects to multiple propagation gates of the plurality of propagation gates and multiple register cells of the plurality of register cells.

Claim 40

The system of claim 30 , wherein each of the entry-point gates is a NAND gate.

Claim 41

The system of claim 30 , wherein each of the entry-point gates is a three-input NAND gate.

Claim 42

The system of claim 31 , wherein the entry-point gates and the propagation gates are the same type of element.

Claim 43

The system of claim 31 , wherein the entry-point gates and the propagation gates are NAND gates.

Claim 46

The method of claim 36 , wherein receiving a clock signal includes receiving the clock signal at all entry-point gate.

Claim 47

The method of claim 36 , wherein propagating the clock signal includes propagating the clock signal through an entry-point gate formed by a NAND gate.

Claim 48

The method of claim 36 , wherein propagating the clock signal includes propagating the clock signal through one or more propagation gates formed by NAND gates.

Claim 49

The method of claim 36 , wherein producing shifting signals includes comparing the external clock signal with a delayed version of the delayed signal.