US6445228B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable even-number clock divider circuit with duty cycle correction and optional phase shift
Assignee: Xilinx Inc
•
Filing: 2001-08-28
•
Granted: 2002-09-03
•
Expires: 2021-08-28
Abstract
Abstract A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.
Inventors
- 👤 Andy T. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:58
CPC Classifications
H; H03; H03K; H03K23/00; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
124 words
A clock divider circuit, comprising: a clock input terminal; a clock output terminal; a state machine having an input terminal coupled to the clock input terminal, and further having set and reset output terminals; a keeper circuit having an output terminal coupled to the clock output terminal; a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal; and a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the state machine, and an output terminal coupled to the clock output terminal.
Claim 2
Dependent Claim
124 words
A clock divider circuit, comprising: a clock input terminal; a clock output terminal; a state machine having an input terminal coupled to the clock input terminal, and further having set and reset output terminals; a keeper circuit having an output terminal coupled to the clock output terminal; a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the state machine, and an output terminal coupled to the clock output terminal; and a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the state machine, and an output terminal coupled to the clock output terminal.
Claim 3
Dependent Claim
67 words
The clock divider circuit of claim 1 , wherein the pullup circuit comprises: a passgate coupled between the clock input terminal and a passgate output terminal, the passgate having a first gate terminal coupled to the set output terminal of the state machine; and a pullup coupled between power high and the clock output terminal, the pullup having a gate terminal coupled to the passgate output terminal.
Claim 4
Dependent Claim
41 words
The clock divider circuit of claim 2 , wherein: the pullup circuit further comprises a first inverter; the pullup is a PMOS transistor; and the gate terminal of the pullup is coupled to the passgate output terminal through the first inverter.
Claim 5
Dependent Claim
43 words
The clock divider circuit of claim 2 , wherein: the pullup circuit further comprises a second inverter; and the passgate is a CMOS passgate having a second gate terminal coupled to the set output terminal of the state machine through the second inverter.
Claim 6
Dependent Claim
66 words
The clock divider circuit of claim 1 , wherein the pulldown circuit comprises: a passgate coupled between the clock input terminal and a passgate output terminal, the passgate having a first gate terminal coupled to the reset output terminal of the state machine; and a pulldown coupled between the clock output terminal and ground, the pulldown having a gate terminal coupled to the passgate output terminal.
Claim 7
Dependent Claim
47 words
The clock divider circuit of claim 5 , wherein: the pulldown circuit further comprises an inverter; the pulldown is an NMOS transistor; and the passgate is a CMOS passgate having a second gate terminal coupled to the reset output terminal of the state machine through the inverter.
Claim 8
Dependent Claim
18 words
The clock divider circuit of claim 1 , wherein the state machine includes a programmable divisor selection circuit.
Claim 9
Dependent Claim
22 words
The clock divider circuit of claim 7 , wherein the clock divider circuit forms a portion of a programmable logic device (PLD).
Claim 10
Dependent Claim
138 words
A programmable clock divider circuit, comprising: a clock input terminal; a clock output terminal; a programmable control circuit having an input terminal coupled to the clock input terminal, and further having set and reset output terminals; a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the programmable control circuit, a set output terminal, and a clock output terminal coupled to the clock output terminal; a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the programmable control circuit, a reset output terminal, and a clock output terminal coupled to the clock output terminal; and a keeper circuit having an output terminal coupled to the clock output terminal.
Claim 11
Dependent Claim
138 words
A programmable clock divider circuit, comprising: a clock input terminal; a clock output terminal; a programmable control circuit having an input terminal coupled to the clock input terminal, and further having set and reset output terminals; a pullup circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the set output terminal of the programmable control circuit, a set output terminal, and a clock output terminal coupled to the clock output terminal; a pulldown circuit having a data input terminal coupled to the clock input terminal, a control input terminal coupled to the reset output terminal of the programmable control circuit, a reset output terminal, and a clock output terminal coupled to the clock output terminal; and a keeper circuit having an output terminal coupled to the clock output terminal.
Claim 12
Dependent Claim
68 words
The clock divider circuit of claim 9 , wherein the pullup circuit comprises: a passgate coupled between the clock input terminal and an output terminal, the passgate having a first gate terminal coupled to the set output terminal of the state machine; and a pullup coupled between power high and the clock output terminal, the pullup having a gate terminal coupled to the output terminal of the passgate.
Claim 13
Dependent Claim
43 words
The clock divider circuit of claim 10 , wherein: the pullup circuit further comprises a first inverter; the pullup is a PMOS transistor; and the gate terminal of the pullup is coupled to the output terminal of the passgate through the first inverter.
Claim 14
Dependent Claim
67 words
The clock divider circuit of claim 9 , wherein the pulldown circuit comprises: a passgate coupled between the clock input terminal and an output terminal, the passgate having a first gate terminal coupled to the reset output terminal of the state machine; and a pulldown coupled between the clock output terminal and ground, the pulldown having a gate terminal coupled to the output terminal of the passgate.
Claim 15
Dependent Claim
36 words
The clock divider circuit of claim 9 , wherein the programmable control circuit comprises: a state machine having set and reset output terminals coupled to the set and reset output terminals of the programmable control circuit.
Claim 16
Dependent Claim
47 words
The clock divider circuit of claim 13 , wherein the programmable control circuit further comprises: a decoder circuit having a plurality of input terminals accepting programming data, and further having a plurality of programming data output terminals coupled to programming data input terminals of the state machine.
Claim 17
Dependent Claim
22 words
The clock divider circuit of claim 14 , wherein the clock divider circuit forms a portion of a programmable logic device (PLD).
Claim 18
Dependent Claim
18 words
The clock divider circuit of claim 15 , wherein the programming data comprises configuration data for the PLD.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |