US7148726B2
Expired / Lapsed
US
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Digital signal buffer circuit
Assignee: Mitsubishi Electric Corp
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Filing: 2004-10-12
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Granted: 2006-12-12
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Expires: 2024-10-12
Abstract
Abstract A delay circuit is provided with a plurality of variously sized equalization transistors, a plurality of equalization resistors having different resistance values, a plurality of equalization capacitors having difference capacitance values, and switch circuits. The switch circuits are used to make selections from among the equalization transistors, equalization resistors, and equalization capacitors for the purpose of adjusting the amplitude level and delay amount of a digital inverse signal.
Inventors
- 👤 Toshihide Oka
- 👤 Hironobu Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:33
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/028; H04L25/0286; H04L25/0288
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
71 words
A digital signal buffer circuit, comprising: an equalization circuit for generating a digital inverse signal that is delayed from an input digital signal and obtained by inverting said input digital signal, wherein said equalization circuit includes a plurality of variously-sized equalization transistors, a delay circuit capable of changing the delay amount, and a switching circuit for switching between said plurality of transistors and changing the delay amount of said delay circuit.
Claim 2
Dependent Claim
71 words
A digital signal buffer circuit, comprising: an equalization circuit for generating a digital inverse signal that is delayed from an input digital signal and obtained by inverting said input digital signal, wherein said equalization circuit includes a plurality of variously-sized equalization transistors, a delay circuit capable of changing the delay amount, and a switching circuit for switching between said plurality of transistors and changing the delay amount of said delay circuit.
Claim 3
Dependent Claim
38 words
The digital signal buffer circuit according to claim 1 , wherein said switching circuit includes a first switch for switching between said plurality of transistors and a second switch for changing the delay amount of said delay circuit.
Claim 4
Dependent Claim
19 words
The digital signal buffer circuit according to claim 2 , wherein said first switch comprises a transfer gate circuit.
Claim 5
Dependent Claim
24 words
The digital signal buffer circuit according to claim 2 , wherein said first switch and said second switch both comprise a transfer gate circuit.
Claim 6
Dependent Claim
56 words
The digital signal buffer circuit according to claim 1 , wherein said delay circuit includes a plurality of equalization resistors having different resistance values and a plurality of equalization capacitors having different capacitance values, and wherein the delay amount is changed by switching between the plurality of equalization resistors and between the plurality of equalization capacitors.
Claim 7
Dependent Claim
38 words
The digital signal buffer circuit according to claim 5 , wherein said switching circuit includes a third switch for switching between said plurality of equalization resistors and a fourth switch for switching between said plurality of equalization capacitors.
Claim 8
Dependent Claim
86 words
The digital signal buffer circuit according to claim 1 , further comprising: an input stage buffer for letting the gates of a pair of transistors receive an input digital signal and an output stage buffer for letting the gates of a pair of transistors receive the output of said input stage buffer, wherein a plurality of transistors in said equalization circuit receive the output of said output stage buffer and apply said digital inverse signal to the gates of the transistors of said output stage buffer.
Claim 9
Dependent Claim
108 words
A digital signal buffer circuit, comprising: a first buffer for receiving an input digital signal; a second buffer for receiving the output of said first buffer; and a third buffer for generating an output digital signal upon receipt of an output from said second buffer, wherein said second buffer includes an equalization transistor, which generates a digital inverse signal that is obtained by inverting said input digital signal and delayed, and switches between a first feedback line for feeding the output of said second buffer back to said equalization transistor and a second feedback line for feeding the output of said third buffer back to said equalization transistor.
Claim 10
Dependent Claim
108 words
A digital signal buffer circuit, comprising: a first buffer for receiving an input digital signal; a second buffer for receiving the output of said first buffer; and a third buffer for generating an output digital signal upon receipt of an output from said second buffer, wherein said second buffer includes an equalization transistor, which generates a digital inverse signal that is obtained by inverting said input digital signal and delayed, and switches between a first feedback line for feeding the output of said second buffer back to said equalization transistor and a second feedback line for feeding the output of said third buffer back to said equalization transistor.
Claim 11
Dependent Claim
30 words
The digital signal buffer circuit according to claim 8 , wherein said first feedback line and said second feedback line are connected to low-pass filters that provide different delay amounts.
Claim 12
Dependent Claim
85 words
A digital signal buffer circuit, comprising: a first buffer for receiving an input digital signal; and a second buffer for generating an output digital signal upon receipt of an output from said first buffer, wherein said second buffer includes an equalization transistor for generating a digital inverse signal that is obtained by inverting said input digital signal and delayed; and wherein a delay path, which includes a switch and a low-pass filter, is formed between the output of said first buffer and said equalization transistor.
Claim 13
Dependent Claim
85 words
A digital signal buffer circuit, comprising: a first buffer for receiving an input digital signal; and a second buffer for generating an output digital signal upon receipt of an output from said first buffer, wherein said second buffer includes an equalization transistor for generating a digital inverse signal that is obtained by inverting said input digital signal and delayed; and wherein a delay path, which includes a switch and a low-pass filter, is formed between the output of said first buffer and said equalization transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-12-11 | 2010-06-12 | 2010-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-12-11 | 2014-06-12 | 2014-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-12-11 | 2018-06-12 | 2018-12-12 | $7700.00 | Window Closed / Lapsed |