Pre-emphasis circuit including slew rate controllable buffer

Claim 2

A pre-emphasis circuit comprising: a first buffer buffering first and second main input signals having phases opposite to each other, outputting first and second main output signals, and controlling slew rates of the first and second main output signals using at least one main control signal; a second buffer buffering first and second sub-input signals having phases opposite to each other, outputting first and second sub-output signals, and controlling slew rates of the first and second sub-output signals using at least one sub-control signal; and an output driver generating first and second output signals having opposite phases using at least two output control signals and the first and second main output signals of the first buffer and the first and second sub-output signals from the second buffer, wherein the first sub-input signal is delayed from the first main input signal by one bit and the second sub-input signal is delayed from the second main input signal by one bit, and wherein the first buffer comprises: a first main input signal processor processing the first main input signal to generate at least two first group gate signals in response to the at least one main control signal; a second main input signal processor processing the second main input signal to generate at least two second group gate signals in response to the at least one main control signal; a first input stage controlling current flowing through the first load resistor connected to a first terminal thereof in response to the first main input signal and the first group gate signals; a second input stage controlling current flowing through the second load resistor connected to a first terminal thereof in response to the second main input signal and the second group gate signals.

Claim 3

The pre-emphasis circuit of claim 1 , further comprising a control circuit outputting the at least one main control signal, the at least one sub-control signal and the at least two control signals.

Claim 4

The pre-emphasis circuit of claim 1 , wherein the first buffer further comprises: a first load resistor having a first terminal connected to a first power supply and a second terminal connected to a second output terminal outputting the second main output signal; a second load resistor having a first terminal connected to the first power supply and a second terminal connected to a first output terminal outputting the first main output signal; and a current source receiving currents flowing through the first and second input stages connected to a first terminal thereof and transferring the received currents to a second power supply.

Claim 5

The pre-emphasis circuit of claim 3 , wherein the first main input signal processor comprises: a first resistor having a first terminal connected to a signal line of the first main input signal and a second terminal connected to a signal line of a first gate signal that is one of the first group gate signals; a second resistor having a first terminal connected to a second terminal of the first resistor and a second terminal connected to a signal line of a second gate signal that is another of the first group gate signals; a first switch switching between the first main input signal and the first gate signal in response to a first main control signal; and a second switch switching between the first main input signal and the second gate signal in response to a second main control signal.

Claim 6

The pre-emphasis circuit of claim 4 , wherein the first input stage comprises: a first MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the second gate signal; a second MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the first gate signal; and a third MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the first main input signal.

Claim 7

The pre-emphasis circuit of claim 5 , wherein the first and second switches are composed of transmission gates, and the first, second and third MOS transistors are NMOS transistors.

Claim 8

The pre-emphasis circuit of claim 3 , wherein the second main input signal processor comprises: a third resistor having a first terminal connected to the signal line of the second main input signal and a second terminal connected to a signal line of a third gate signal that is one of the second group gate signals; a fourth resistor having a first terminal connected to a second terminal of the third resistor and a second terminal connected to a signal line of a fourth gate signal that is another of the second group gate signals; a third switch switching between the second main input signal and the third gate signal in response to a first main control signal; and a fourth switch switching between the second main input signal and the fourth gate signal in response to a second main control signal.

Claim 9

The pre-emphasis circuit of claim 7 , wherein the second input stage comprises: a fourth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the fourth gate signal; a fifth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the third gate signal; and a sixth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the second main input signal.

Claim 10

The pre-emphasis circuit of claim 8 , wherein the third and fourth switches are composed of transmission gates, and the fourth, fifth and sixth MOS transistors are NMOS transistors.

Claim 11

A pre-emphasis circuit comprising: a first buffer buffering first and second main input signals having phases opposite to each other, outputting first and second main output signals, and controlling slew rates of the first and second main output signals using at least one main control signal; a second buffer buffering first and second sub-input signals having phases opposite to each other, outputting first and second sub-output signals, and controlling slew rates of the first and second sub-output signals using at least one sub-control signal; and an output driver generating first and second output signals having opposite phases using at least two output control signals and the first and second main output signals of the first buffer and the first and second sub-output signals from the second buffer, wherein the first sub-input signal is delayed from the first main input signal by one bit and the second sub-input signal is delayed from the second main input signal by one bit, and wherein the second buffer comprises: a first load resistor having a first terminal connected to the first power supply and a second terminal connected to a second output terminal outputting the second sub-output signal; a second load resistor having a first terminal connected to the first power supply and a second terminal connected to a first output terminal outputting the first sub-output signal; a first sub-input signal processor processing the first sub-input signal to generate at least two first group gate signals in response to the at least one sub-control signal; a second sub-input signal processor processing the second sub-input signal to generate at least two second group gate signals in response to the at least one sub-control signal; a first input stage controlling current flowing through the first load resistor connected to a first terminal thereof in response to the first group gate signals; a second input stage controlling current flowing through the second load resistor connected to a first terminal thereof in response to the second group gate signals; and a current source receiving currents flowing through the first and second input stages connected to a first terminal thereof and transferring the received currents to a second power supply.

Claim 12

A pre-emphasis circuit comprising: a first buffer buffering first and second main input signals having phases opposite to each other, outputting first and second main output signals, and controlling slew rates of the first and second main output signals using at least one main control signal; a second buffer buffering first and second sub-input signals having phases opposite to each other, outputting first and second sub-output signals, and controlling slew rates of the first and second sub-output signals using at least one sub-control signal; and an output driver generating first and second output signals having opposite phases using at least two output control signals and the first and second main output signals of the first buffer and the first and second sub-output signals from the second buffer, wherein the first sub-input signal is delayed from the first main input signal by one bit and the second sub-input signal is delayed from the second main input signal by one bit, and wherein the second buffer comprises: a first load resistor having a first terminal connected to the first power supply and a second terminal connected to a second output terminal outputting the second sub-output signal; a second load resistor having a first terminal connected to the first power supply and a second terminal connected to a first output terminal outputting the first sub-output signal; a first sub-input signal processor processing the first sub-input signal to generate at least two first group gate signals in response to the at least one sub-control signal; a second sub-input signal processor processing the second sub-input signal to generate at least two second group gate signals in response to the at least one sub-control signal; a first input stage controlling current flowing through the first load resistor connected to a first terminal thereof in response to the first group gate signals; a second input stage controlling current flowing through the second load resistor connected to a first terminal thereof in response to the second group gate signals; and a current source receiving currents flowing through the first and second input stages connected to a first terminal thereof and transferring the received currents to a second power supply.

Claim 13

The pre-emphasis circuit of claim 10 , wherein the first sub-input signal processor comprises: a first resistor having a first terminal connected to a signal line of the first sub-input signal and a second terminal connected to a signal line of a first gate signal that is one of the first group gate signals; a second resistor having a first terminal connected to a second terminal of the first resistor and a second terminal connected to a signal line of a second gate signal that is another of the first group gate signals; a first switch switching between the first sub-input signal and the first gate signal in response to a first sub-control signal; and a second switch switching between the first sub-input signal and the second gate signal in response to a second sub-control signal.

Claim 14

The pre-emphasis circuit of claim 11 , wherein the first input stage comprises: a first MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the second gate signal; a second MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the first gate signal; and a third MOS transistor having a first terminal connected to the second output terminal, a second terminal connected to the current source, and a gate receiving the first sub-input signal.

Claim 15

The pre-emphasis circuit of claim 12 , wherein the first and second switches are composed of transmission gates, and the first, second and third MOS transistors are NMOS transistors.

Claim 16

The pre-emphasis circuit of claim 10 , wherein the second sub-input signal processor comprises: a third resistor having a first terminal connected to a signal line of the second sub-input signal and a second terminal connected to a signal line of a third gate signal that is one of the second group gate signals; a fourth resistor having a first terminal connected to a second terminal of the third resistor and a second terminal connected to a signal line of a fourth gate signal that is another of the second group gate signals; a third switch switching between the second sub-input signal and the third gate signal in response to a first sub-control signal; and a fourth switch switching between the second sub-input signal and the fourth gate signal in response to a second sub-control signal.

Claim 17

The pre-emphasis circuit of claim 14 , wherein the second input stage comprises: a fourth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the fourth gate signal; a fifth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the third gate signal; and a sixth MOS transistor having a first terminal connected to the first output terminal, a second terminal connected to the current source, and a gate receiving the second sub-input signal.

Claim 18

The pre-emphasis circuit of claim 15 , wherein the third and fourth switches are composed of transmission gates, and the fourth, fifth and sixth MOS transistors are NMOS transistors.