Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock

Claim 2

A delay locked loop, comprising: a delay line configured to receive a reference signal and generate a delayed signal at a frequency and a delay amount; a feedback loop including a frequency divider operably coupled to the delay line and configured to receive the delayed signal and output a frequency divided signal at another frequency substantially equal to the frequency divided by an integer; and a phase detector configured to receive the reference signal and the frequency divided signal, measure a phase difference between the reference signal and the frequency divided signal, and adjust the delay amount responsive to the measured phase difference; wherein the phase detector is configured to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal if the integer is equal to an odd number and activate upon detection of the rising edge of the frequency divided signal if the integer is equal to an even number.

Claim 3

The delay locked loop of claim 1 , wherein the another frequency is substantially equal to the frequency divided by one of two, four, and six.

Claim 4

The delay locked loop of claim 1 , wherein the another frequency is substantially equal to the frequency divided by one of three, five, and seven.

Claim 5

The delay locked loop of claim 1 , wherein the phase detector is configured to wait a number of clock cycles after enabling the feedback loop before measuring the phase difference between the reference signal and the frequency divided signal.

Claim 6

The delay locked loop of claim 1 , wherein the frequency divided signal is configured as a master control clock.

Claim 7

The delay locked loop of claim 1 , wherein the phase detector is configured to receive a register command used to program the phase detector to measure the phase difference between the external signal and the frequency divided signal in response to receipt of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and in response to receipt of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 8

The delay locked loop of claim 1 , further comprising a divided internal clock driven by the frequency divided signal.

Claim 9

The delay locked loop of claim 1 , wherein the frequency divider is hardwired to perform frequency division by a determined amount.

Claim 10

The delay locked loop of claim 1 , wherein the frequency divider is configured to receive a register command indicating an amount of frequency division to be performed.

Claim 11

The delay locked loop of claim 1 , wherein the phase detector is hardwired to measure the phase difference between the external signal and the frequency divided signal in response to receipt of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and in response to receipt of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 14

The method of claim 11 , wherein generating the frequency divided signal comprises generating a frequency divided signal having another frequency that is substantially equal to one of one-half and one-fourth of the frequency.

Claim 15

The method of claim 11 , wherein generating the frequency divided signal comprises generating a frequency divided signal having another frequency that is substantially equal to one-third of the frequency.

Claim 16

The method of claim 11 , further comprising hardwiring the phase detector to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal if the integer is equal to an odd number and activate upon detection of the rising edge of the frequency divided signal if the integer is equal to an even number.

Claim 17

The method of claim 11 , further comprising programming the phase detector with a register command to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal if the integer is equal to an odd number and activate upon detection of the rising edge of the frequency divided signal if the integer is equal to an even number.

Claim 20

The method of claim 16 , further comprising hardwiring the phase detector to activate with each of a rising edge and a falling edge of the feedback signal if the integer is equal to an odd number and activate with the rising edge of the feedback signal if the integer is equal to an even number.

Claim 21

The method of claim 16 , further comprising programming the phase detector with a register command to activate with each of a rising edge and a falling edge of the feedback signal if the integer is equal to an odd number and activate with the rising edge of the feedback signal if the integer is equal to an even number.

Claim 22

A semiconductor device, comprising: at least one delay locked loop comprising: a forward path adapted to receive an external signal and generate a delayed signal at a frequency; a feedback loop operably coupled to the forward path and adapted to receive the delayed signal and generate a frequency divided signal having another frequency substantially equal to the frequency divided by an integer; and a phase detector adapted to receive the external signal and the frequency divided signal and generate a control signal related to a phase comparison of the reference signal and the frequency divided signal; wherein the phase detector is configured to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and activate upon detection of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 23

A semiconductor device, comprising: at least one delay locked loop comprising: a forward path adapted to receive an external signal and generate a delayed signal at a frequency; a feedback loop operably coupled to the forward path and adapted to receive the delayed signal and generate a frequency divided signal having another frequency substantially equal to the frequency divided by an integer; and a phase detector adapted to receive the external signal and the frequency divided signal and generate a control signal related to a phase comparison of the reference signal and the frequency divided signal; wherein the phase detector is configured to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and activate upon detection of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 24

The semiconductor device of claim 19 , wherein the feedback loop comprises a frequency divider adapted to generate the frequency divided signal.

Claim 25

The semiconductor device of claim 19 , wherein phase detector is configured to be programmed with a register command to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and activate upon detection of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 26

The semiconductor device of claim 19 , wherein phase detector is hardwired to activate upon detection of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and activate upon detection of a rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 27

An electronic system, comprising: at least one processor; at least one memory device; and at least one delay lock loop operably associated with the at least one memory device and comprising: a delay line operably coupled between an input and an output and adapted to receive an external signal and generate a delayed signal in response to receipt of the external signal; a frequency divider operably coupled to the delay line and configured to generate a frequency divided signal in response to receipt of the delayed signal, wherein a frequency of the frequency divided signal is substantially equal to the frequency divided by an integer; and a phase detector operably coupled to the input and the frequency divider and configured to measure a phase difference between the external signal and the frequency divided signal in response to receipt of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and in response to receipt of the rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 28

An electronic system, comprising: at least one processor; at least one memory device; and at least one delay lock loop operably associated with the at least one memory device and comprising: a delay line operably coupled between an input and an output and adapted to receive an external signal and generate a delayed signal in response to receipt of the external signal; a frequency divider operably coupled to the delay line and configured to generate a frequency divided signal in response to receipt of the delayed signal, wherein a frequency of the frequency divided signal is substantially equal to the frequency divided by an integer; and a phase detector operably coupled to the input and the frequency divider and configured to measure a phase difference between the external signal and the frequency divided signal in response to receipt of each of a rising edge and a falling edge of the frequency divided signal when the integer is equal to an odd number and in response to receipt of the rising edge of the frequency divided signal when the integer is equal to an even number.

Claim 29

The electronic system of claim 23 , wherein the delay locked loop is positioned within the at least one memory device.

Claim 30

The electronic system of claim 23 , wherein the delay locked loop is positioned within a memory controller operably coupled to the at least one memory device.