System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits

Claim 1

A method for compensating for variance from a relationship between a first delay and a second delay the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a signal indicative of the relationship between the first delay and the second delay; stabilizing the signal, the stabilized signal for use as the control signal for the adjustable delay; and adjusting in accordance with the stabilized signal a parameter affecting the relationship between the first delay and the second delay in response to the determined relationship being outside a variance range by setting a transition point at which a variable delay line having a plurality of first delay circuits and having a plurality of second delay circuits switches from a first delay circuit of the plurality to a second delay circuit of the plurality in accordance with the stabilized signal when the first and second delayed clock signals are in phase.

Claim 2

A method for compensating for variance from a relationship between a first delay and a second delay the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a signal indicative of the relationship between the first delay and the second delay; stabilizing the signal, the stabilized signal for use as the control signal for the adjustable delay; and adjusting in accordance with the stabilized signal a parameter affecting the relationship between the first delay and the second delay in response to the determined relationship being outside a variance range by setting a transition point at which a variable delay line having a plurality of first delay circuits and having a plurality of second delay circuits switches from a first delay circuit of the plurality to a second delay circuit of the plurality in accordance with the stabilized signal when the first and second delayed clock signals are in phase.

Claim 6

A method for compensating for variance from a relationship between a fine delay and a coarse delay of a variable delay line, the method comprising: determining a current relationship between the fine delay and the coarse delay; generating a compensation signal representing the current relationship between the fine delay and the coarse delay; stabilizing the compensation signal by ignoring at least one transition of the compensation signal occurring within at least one period of an input clock signal to provide a stabilized compensation signal; and setting in accordance with the stabilized compensation signal a transition point at which the variable delay line switches from a fine delay to a coarse delay based on the current determined relationship to compensate for the variance.

Claim 7

A method for compensating for variance from a relationship between a fine delay and a coarse delay of a variable delay line, the method comprising: determining a current relationship between the fine delay and the coarse delay; generating a compensation signal representing the current relationship between the fine delay and the coarse delay; stabilizing the compensation signal by ignoring at least one transition of the compensation signal occurring within at least one period of an input clock signal to provide a stabilized compensation signal; and setting in accordance with the stabilized compensation signal a transition point at which the variable delay line switches from a fine delay to a coarse delay based on the current determined relationship to compensate for the variance.

Claim 11

A method for determining a relationship between a first delay and a second delay, the first delay less than the second delay, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and a second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a phase adjustment signal indicative of the phase relationship for use as the control signal for the adjustable delay, the phase adjustment signal further indicative of the relationship between the first delay and the second delay when the first and second delayed clock signals are in phase; filtering the phase adjustment signal to reduce rippling of the phase adjustment signal; and setting a transition point at which a variable delay line having a plurality of first delay circuits having the first delay and a plurality of second delay circuits having the second delay switches from a first delay of the plurality circuit to a second delay circuit of the plurality in accordance with the phase adjustment signal when the first and second delayed lock signals are in phase.

Claim 12

A method for determining a relationship between a first delay and a second delay, the first delay less than the second delay, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and a second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a phase adjustment signal indicative of the phase relationship for use as the control signal for the adjustable delay, the phase adjustment signal further indicative of the relationship between the first delay and the second delay when the first and second delayed clock signals are in phase; filtering the phase adjustment signal to reduce rippling of the phase adjustment signal; and setting a transition point at which a variable delay line having a plurality of first delay circuits having the first delay and a plurality of second delay circuits having the second delay switches from a first delay of the plurality circuit to a second delay circuit of the plurality in accordance with the phase adjustment signal when the first and second delayed lock signals are in phase.

Claim 18

A method for determining a relationship between a fine delay of a fine delay circuit and a coarse delay of a coarse delay circuit, the method comprising: determining a phase relationship between a reference delay clock signal and an adjustable delay clock signal, the reference delay clock signal delayed from an input clock signal by the fine delay and the coarse delay and the adjustable delay clock signal delayed from the input clock signal by an adjustable time delay; generating a compensation signal based on the phase relationship between the reference delay clock signal and the adjustable delay clock signal; ignoring transitions of the compensation signal occurring within at least one period of the input clock signal to provide a filtered compensation signal; and adjusting the adjustable time delay to correct for the phase difference between the reference delay clock signal and the adjustable delay clock signal responsive to the filtered compensation signal, the resulting filtered compensation signal at phase lock representative of a ratio between the fine delay of the fine delay circuit and the coarse delay of the coarse delay circuit.

Claim 19

A method for determining a relationship between a fine delay of a fine delay circuit and a coarse delay of a coarse delay circuit, the method comprising: determining a phase relationship between a reference delay clock signal and an adjustable delay clock signal, the reference delay clock signal delayed from an input clock signal by the fine delay and the coarse delay and the adjustable delay clock signal delayed from the input clock signal by an adjustable time delay; generating a compensation signal based on the phase relationship between the reference delay clock signal and the adjustable delay clock signal; ignoring transitions of the compensation signal occurring within at least one period of the input clock signal to provide a filtered compensation signal; and adjusting the adjustable time delay to correct for the phase difference between the reference delay clock signal and the adjustable delay clock signal responsive to the filtered compensation signal, the resulting filtered compensation signal at phase lock representative of a ratio between the fine delay of the fine delay circuit and the coarse delay of the coarse delay circuit.

Claim 24

A method for compensating for variance from a relationship between a first delay of a first delay circuit and a second delay of a second delay circuit, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a signal indicative of the relationship between the first delay and the second delay; stabilizing the signal by ignoring at least some transitions of the generated signal, the stabilized signal for use as the control signal for the adjustable delay; and adjusting in accordance with the stabilized signal a parameter affecting the relationship between the first delay and the second delay in response to the determined relationship being outside a variance range.

Claim 25

A method for compensating for variance from a relationship between a first delay of a first delay circuit and a second delay of a second delay circuit, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and second reference delay; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a signal indicative of the relationship between the first delay and the second delay; stabilizing the signal by ignoring at least some transitions of the generated signal, the stabilized signal for use as the control signal for the adjustable delay; and adjusting in accordance with the stabilized signal a parameter affecting the relationship between the first delay and the second delay in response to the determined relationship being outside a variance range.

Claim 29

A method for determining a relationship between a first delay and a second delay, the first delay less than the second delay, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and a second reference delays; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a phase adjustment signal indicative of the phase relationship for use as the control signal for the adjustable delay, the phase adjustment signal further indicative of the relationship between the first delay and the second delay when the first and second delayed clock signals are in phase; and filtering the phase adjustment signal to reduce rippling of the phase adjustment signal by ignoring transitions of the phase adjustment signal within at least one clock period.

Claim 30

A method for determining a relationship between a first delay and a second delay, the first delay less than the second delay, the method comprising: delaying a clock signal by a reference delay to provide a first delayed clock signal, the reference time delay equal the total delay of a first reference delay and a second reference delays; delaying the clock signal by an adjustable delay to provide a second delayed clock signal, the adjustable delay set by a control signal; determining a phase relationship between the first and second delayed clock signals; generating a phase adjustment signal indicative of the phase relationship for use as the control signal for the adjustable delay, the phase adjustment signal further indicative of the relationship between the first delay and the second delay when the first and second delayed clock signals are in phase; and filtering the phase adjustment signal to reduce rippling of the phase adjustment signal by ignoring transitions of the phase adjustment signal within at least one clock period.