Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution

Claim 3

The device of claim 1 , wherein the receiving circuitry comprises a plurality of delay elements and interpolation circuitry coupled thereto.

Claim 4

The device of claim 2 , wherein the interpolation circuitry comprises a plurality of buffers, at least two of which have outputs coupled to an input of another of the plurality of buffers.

Claim 5

The device of claim 1 , wherein the comparing circuitry comprises a phase detector for outputting count-up and count-down control signals.

Claim 6

The device of claim 1 , wherein the device comprises a delay locked loop (DLL).

Claim 7

The device of claim 1 , wherein at least one of the first and second output signals comprises a quadrature clock.

Claim 8

The device of claim 1 , wherein the input signal comprises an input clock.

Claim 9

A delay locked loop configured to output at least a first and a second output clock signals, the delay locked loop comprising: a plurality of delay elements having at least one delay element configured to receive an input clock signal and in combination output a first series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the first series; a phase detector configured to compare relative phases of the first output clock signal and the input clock signal and to output control signals in response to relative differences between the compared relative phases; first and second counters coupled to the phase detector and configured to output respective first and second count signals in response to the control signals; a first multiplexer coupled to each of the plurality of delay elements and the first counter, the first multiplexer configured to select and output the first output clock signal from among the first series of delayed clock signals in accordance with the first count signal; interpolation circuitry coupled to the plurality of delay elements and configured to produce a plurality of interpolated clock signals, the interpolation circuitry further configured to receive a portion of the first series of delayed clock signals and provide the plurality of interpolated clock signals and to output a second series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the second series; and a second multiplexer coupled to the interpolation circuitry and to the second counter, the second multiplexer configured to select and output the second output clock signal from among the second series of delayed clock signals in accordance with the second count signal.

Claim 10

A delay locked loop configured to output at least a first and a second output clock signals, the delay locked loop comprising: a plurality of delay elements having at least one delay element configured to receive an input clock signal and in combination output a first series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the first series; a phase detector configured to compare relative phases of the first output clock signal and the input clock signal and to output control signals in response to relative differences between the compared relative phases; first and second counters coupled to the phase detector and configured to output respective first and second count signals in response to the control signals; a first multiplexer coupled to each of the plurality of delay elements and the first counter, the first multiplexer configured to select and output the first output clock signal from among the first series of delayed clock signals in accordance with the first count signal; interpolation circuitry coupled to the plurality of delay elements and configured to produce a plurality of interpolated clock signals, the interpolation circuitry further configured to receive a portion of the first series of delayed clock signals and provide the plurality of interpolated clock signals and to output a second series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the second series; and a second multiplexer coupled to the interpolation circuitry and to the second counter, the second multiplexer configured to select and output the second output clock signal from among the second series of delayed clock signals in accordance with the second count signal.

Claim 11

A Synchronous Dynamic Random Access Memory (SDRAM) including a delay locked loop (DLL) for outputting first and second output clock signals, each lagging an input clock signal by a controlled amount different than the other, the Dll comprising: circuitry configured to receive the input clock signal and output a first series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed clock signals including a portion of the first series and a plurality of clocks interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output clock signal and the input clock signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output clock signals from among the respective first and second series of delayed clock signals in response to the control signals.

Claim 12

A Synchronous Dynamic Random Access Memory (SDRAM) including a delay locked loop (DLL) for outputting first and second output clock signals, each lagging an input clock signal by a controlled amount different than the other, the Dll comprising: circuitry configured to receive the input clock signal and output a first series of delayed clock signals, each delayed clock signal lagging the input clock signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed clock signals including a portion of the first series and a plurality of clocks interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output clock signal and the input clock signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output clock signals from among the respective first and second series of delayed clock signals in response to the control signals.

Claim 13

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, processor, and memory devices including a device for outputting first and second output signals, the device comprising: circuitry configured to receive an input signal and output a first series of delayed signals, each delayed signal lagging the input signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed signals including a portion of the first series and a plurality of signals interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.

Claim 14

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, processor, and memory devices including a device for outputting first and second output signals, the device comprising: circuitry configured to receive an input signal and output a first series of delayed signals, each delayed signal lagging the input signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed signals including a portion of the first series and a plurality of signals interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.

Claim 15

The electronic system of claim 10 , wherein the electronic system comprises a computer system.

Claim 16

The electronic system of claim 10 , wherein the memory device comprises a Synchronous Dynamic Random Access Memory (SDRAM).

Claim 17

A semiconductor substrate having a device fabricated on a surface thereof for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry configured to receive an input signal and output a first series of delayed signals, each delayed signal lagging the input signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed signals including a portion of the first series and a plurality of signals interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.

Claim 18

A semiconductor substrate having a device fabricated on a surface thereof for outputting first and second output signals, each lagging an input signal by a controlled amount different than the other, the device comprising: circuitry configured to receive an input signal and output a first series of delayed signals, each delayed signal lagging the input signal more than its predecessor in the first series, the circuitry further configured to receive a second series of delayed signals including a portion of the first series and a plurality of signals interpolated therefrom; circuitry configured to compare relative phases of at least one of the first and second output signals and the input signal and outputting control signals in accordance therewith; and circuitry coupled to the receiving circuitry and the comparing circuitry for selecting and outputting the first and second output signals from among the respective first and second series of delayed signals in response to the control signals.

Claim 19

The semiconductor substrate of claim 13 , wherein the semiconductor substrate comprises a semiconductor wafer.

Claim 22

The method of claim 15 , wherein the generating the first and second series of delayed signals comprise generating said series using a plurality of delay elements and interpolation circuitry.

Claim 25

The method of claim 17 , wherein the off-phase clock signal is a quadrature clock signal.

Claim 26

The method of claim 17 , wherein selecting and outputting the first and second output signals from among the respective first and second series of delayed signals comprises selecting a first signal from the first series of delayed signals which is 180° out of phase with the input signal and a second signal from the second series of delayed signals which is 90° out of phase with the input signal.