Patent US8350389B2 successfully refreshed from Google Patents.
US8350389B2
Active / In Force
US
⏱️ 3.9 years remaining
Semiconductor device and information processing system including the same
Assignee: Longitude Licensing Ltd
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Filing: 2010-10-07
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Granted: 2013-01-08
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Expires: 2030-10-07
Abstract
Abstract A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
Inventors
- 👤 Satoshi Itaya
- 👤 Kayoko Shibata
- 👤 Shoji Azuma
- 👤 Akira Ide
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0242; H10W20/20; H10W20/211; H10W20/213; H10W20/2134; H10W20/217; H10W72/00; H10W72/01; H10W72/012; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W90/00; H10W90/701; H10W72/019; H10W72/20; H10W72/221; H10W72/222; H10W72/227; H10W72/241; H10W72/242; H10W72/251; H10W72/29; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/921; H10W72/926; H10W74/111; H10W74/114; H10W74/117; H10W90/20; H10W90/297; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
126 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes that penetrate the semiconductor substrate; first and second wiring pads respectively connected to the first and second penetration electrodes, wherein the first penetration electrode is supplied with a signal, the second penetration electrode is supplied with a power source potential, and the second wiring pad has larger size than the first wiring pad; and a signal wiring, wherein a plurality of the second wiring pads are provided on different wiring layers from each other, the signal wiring is provided on a same wiring layer as one of the second wiring pads, and at least a part of the signal wiring is overlapped with other one of the second wiring pads in a planar view.
Claim 2
Dependent Claim
126 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes that penetrate the semiconductor substrate; first and second wiring pads respectively connected to the first and second penetration electrodes, wherein the first penetration electrode is supplied with a signal, the second penetration electrode is supplied with a power source potential, and the second wiring pad has larger size than the first wiring pad; and a signal wiring, wherein a plurality of the second wiring pads are provided on different wiring layers from each other, the signal wiring is provided on a same wiring layer as one of the second wiring pads, and at least a part of the signal wiring is overlapped with other one of the second wiring pads in a planar view.
Claim 3
Dependent Claim
77 words
A semiconductor device comprising: a semiconductor substrate; first and second bumps provided over the semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate; a first conductive structure making a first electrical path between the first bump and the first penetration electrode; and a second conductive structure making a second electrical path between the second bump and the second penetration electrode; the second conductive structure being smaller in resistance value than the first conductive structure.
Claim 4
Dependent Claim
77 words
A semiconductor device comprising: a semiconductor substrate; first and second bumps provided over the semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate; a first conductive structure making a first electrical path between the first bump and the first penetration electrode; and a second conductive structure making a second electrical path between the second bump and the second penetration electrode; the second conductive structure being smaller in resistance value than the first conductive structure.
Claim 5
Dependent Claim
24 words
The semiconductor device as claimed in claim 2 , wherein the first and second bumps are substantially the same in size as each other.
Claim 6
Dependent Claim
24 words
The semiconductor device as claimed in claim 3 , wherein the first and second penetration electrodes are the same in size as each other.
Claim 7
Dependent Claim
97 words
The semiconductor device as claimed in claim 2 , wherein the first conductive structure further includes a plurality of first pads stacked with one another such that vertically adjacent two of the first pads are connected via at least one first through electrode and the second conductive structure further includes a plurality of second pads stacked with one another such that vertically adjacent two of the second pads are connected via at least one second through electrode and at least one of the second pads is larger in size than at least one of the first pads.
Claim 8
Dependent Claim
20 words
The semiconductor device as claimed in claim 2 , further comprising a plurality of transistors provided on the semiconductor substrate.
Claim 9
Dependent Claim
40 words
The semiconductor device as claimed in claim 2 , further comprising first and second insulating rings each surrounding an associated one of the first and second penetration electrodes to electrically separate the first penetration electrode from the second penetration electrode.
Claim 10
Dependent Claim
63 words
The semiconductor device as claimed in claim 2 , wherein the first and second penetration electrodes includes top surfaces coupled to the first and second conductive structures, respectively, and bottom surfaces, the semiconductor device further comprises a third bump provided on the bottom surface of the first penetration electrode and a fourth bump provided on the bottom surface of the second penetration electrode.
Claim 11
Dependent Claim
24 words
The semiconductor device as claimed in claim 8 , wherein the third and fourth bumps are substantially the same in size as each other.
Claim 12
Dependent Claim
167 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate: a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring; a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode; a second wiring pad formed as the upper-level wiring; a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads; a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode; a fourth wiring pad formed as the upper-level wiring; and a plurality of second through electrodes each formed in the interlayer insulating film to form an electrical connection between the third and fourth wiring pads, wherein the first wiring pad is greater in size than the third wiring pad.
Claim 13
Dependent Claim
167 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate: a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring; a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode; a second wiring pad formed as the upper-level wiring; a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads; a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode; a fourth wiring pad formed as the upper-level wiring; and a plurality of second through electrodes each formed in the interlayer insulating film to form an electrical connection between the third and fourth wiring pads, wherein the first wiring pad is greater in size than the third wiring pad.
Claim 14
Dependent Claim
23 words
The semiconductor device as claimed in claim 10 , wherein the first through electrodes are greater in number than the second through electrodes.
Claim 15
Dependent Claim
23 words
The semiconductor device as claimed in claim 10 , wherein the first wiring pad is greater in size than the second wiring pad.
Claim 16
Dependent Claim
33 words
The semiconductor device as claimed in claim 10 , further comprising: first and second insulation rings each penetrating the semiconductor substrate to surround an associated one of the first and second penetration electrodes.
Claim 17
Dependent Claim
43 words
The Semiconductor device as claimed in claim 13 , wherein the semiconductor substrate includes an active region between the first and second insulation rings, and the semiconductor device further comprises at least one transistor formed in the active region of the semiconductor substrate.
Claim 18
Dependent Claim
25 words
The semiconductor device as claimed in claim 10 , wherein the first and second penetration electrodes are substantially the same in size as each other.
Claim 19
Dependent Claim
37 words
The semiconductor device as claimed in claim 10 , wherein the first penetration electrode is configured to be supplied with a power source voltage and the second penetration electrode is configured to be supplied with a signal.
Claim 20
Dependent Claim
77 words
The semiconductor device as claimed in claim 10 , wherein the first and second penetration electrodes are coupled to the first and second wiring pads at top surfaces thereof, respectively, and wherein the semiconductor device further comprises: a first bump connected to a bottom surface of the first penetration electrode; and a second bump connected to a bottom surface of the second penetration electrode, the second bump being substantially the same in size as the first bump.
Claim 21
Dependent Claim
62 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate; and first and second wiring pads respectively connected to the first and second penetration electrodes, wherein the first and second penetration electrodes are substantially the same in size as each other and the first and second wiring pads are different in size from each other.
Claim 22
Dependent Claim
62 words
A semiconductor device comprising: a semiconductor substrate; first and second penetration electrodes each penetrating the semiconductor substrate; and first and second wiring pads respectively connected to the first and second penetration electrodes, wherein the first and second penetration electrodes are substantially the same in size as each other and the first and second wiring pads are different in size from each other.
Claim 23
Dependent Claim
77 words
The semiconductor device as claimed in claim 18 , wherein the first and second penetration electrodes are coupled to the first and second wiring pads at top surfaces thereof, respectively, and wherein the semiconductor device further comprises: a first bump connected to a bottom surface of the first penetration electrode; and a second bump connected to a bottom surface of the second penetration electrode, the second bump being substantially the same in size as the first bump.
Claim 24
Dependent Claim
33 words
The semiconductor device as claimed in claim 18 , further comprising: first and second insulation rings each penetrating the semiconductor substrate to surround an associated one of the first and second penetration electrodes.
Claim 25
Dependent Claim
43 words
The semiconductor device as claimed in claim 20 , wherein the semiconductor substrate includes an active region between the first and second insulation rings, and the semiconductor device further comprises at least one transistor formed in the active region of the semiconductor substrate.
Claim 26
Dependent Claim
37 words
The semiconductor device as claimed in claim 18 , wherein the first penetration electrode is configured to be supplied with a power source voltage and the second penetration electrode is configured to be supplied with a signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2016-01-08 | 2016-07-09 | 2017-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2020-01-08 | 2020-07-09 | 2021-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2024-01-08 | 2024-07-09 | 2025-01-08 | $7700.00 | Window Closed / Lapsed |