US5466893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Printed circuit board having enhanced EMI suppression
Assignee: Nintendo Co Ltd
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Filing: 1994-03-30
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Granted: 1995-11-14
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Expires: 2014-03-30
Abstract
Abstract The radiation noise suppression effect is enhanced by providing an insulation layer which is formed so that the circuit pattern is covered excepting at least a part of power source pattern or ground pattern on the substrate on which circuit pattern is formed, and a conductive layer which is formed so as to be connected to the uninsulated part of the power source pattern or the ground pattern on the insulation layer, by modifying pattern shape of the conductive layer and the insulation layer or by increasing or reducing the number of these layers.
Inventors
- 👤 Fumio Nakatani
- 👤 Shinichi Wakita
- 👤 Hisatoshi Murakami
- 👤 Tsunehiko Terada
- 👤 Shohei Morimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:50
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/0218; H05K1/0254; H05K1/0257; H05K1/0259; H05K3/00; H05K3/40; H05K3/42; H05K3/429; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09236; H05K2201/0929; H05K2201/093; H05K2201/09654; H05K2201/09663; H05K2201/0969; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10689
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
151 words
A printed circuit board, comprising: a substrate, including a plurality of through-holes; a circuit pattern formed on the substrate, the circuit pattern including a signal line pattern and a reference potential setting line pattern in which a reference potential is set for the signal line pattern, said circuit pattern also including a plurality of IC pin lands surrounding said through-holes of said substrate to receive IC pins; an insulation layer formed on the substrate so as to cover the circuit pattern excepting at least a part of the reference potential setting line pattern; and a conductive layer formed on the insulation layer so as to be connected to an uninsulated part of the reference potential setting line pattern, said conductive layer overlying at least a portion of said substrate and said circuit pattern between said plurality of IC pin lands and the pin insertion through-holes without contacting an IC pin land.
Claim 2
Dependent Claim
151 words
A printed circuit board, comprising: a substrate, including a plurality of through-holes; a circuit pattern formed on the substrate, the circuit pattern including a signal line pattern and a reference potential setting line pattern in which a reference potential is set for the signal line pattern, said circuit pattern also including a plurality of IC pin lands surrounding said through-holes of said substrate to receive IC pins; an insulation layer formed on the substrate so as to cover the circuit pattern excepting at least a part of the reference potential setting line pattern; and a conductive layer formed on the insulation layer so as to be connected to an uninsulated part of the reference potential setting line pattern, said conductive layer overlying at least a portion of said substrate and said circuit pattern between said plurality of IC pin lands and the pin insertion through-holes without contacting an IC pin land.
Claim 3
Dependent Claim
20 words
A printed circuit board according to claim 1, wherein said reference potential setting line pattern is a ground line pattern.
Claim 4
Dependent Claim
20 words
A printed circuit board according to claim 1, wherein said reference potential setting line pattern is a power line pattern.
Claim 5
Dependent Claim
25 words
A printed circuit board according to claim 1, wherein said signal line pattern includes a bent part having an interior angle of at least 135°.
Claim 6
Dependent Claim
26 words
A printed circuit board according to claim 1, wherein said signal line pattern includes a bent part in said circuit pattern defined by a circular arc.
Claim 7
Dependent Claim
26 words
A printed circuit board according to claim 1, wherein said insulation layer is a resin insulation material and said conductive layer is a cured conductive paste.
Claim 8
Independent Claim
168 words
A method of forming a printed circuit board, comprising: forming a substrate including a plurality of through-holes; forming a circuit pattern on the substrate, the circuit pattern including a signal line pattern and a reference potential setting line pattern in which a reference potential is set for the signal line pattern, said circuit pattern also including a plurality of IC pin lands surrounding said through-holes of said substrate to receive IC pins; applying an insulation layer on the substrate by a screen printing process so as to cover the circuit pattern excepting at least a part of the reference potential setting line pattern; and covering the insulation layer with a conductive layer applied by a screen printing process, the insulation layer connected to an uninsulated part of the reference potential setting line pattern, the conductive layer overlying at least a portion of said substrate and said circuit pattern between said plurality of IC pin lands and the pin insertion through-holes without contacting any of the IC pin lands.
Claim 9
Independent Claim
168 words
A method of forming a printed circuit board, comprising: forming a substrate including a plurality of through-holes; forming a circuit pattern on the substrate, the circuit pattern including a signal line pattern and a reference potential setting line pattern in which a reference potential is set for the signal line pattern, said circuit pattern also including a plurality of IC pin lands surrounding said through-holes of said substrate to receive IC pins; applying an insulation layer on the substrate by a screen printing process so as to cover the circuit pattern excepting at least a part of the reference potential setting line pattern; and covering the insulation layer with a conductive layer applied by a screen printing process, the insulation layer connected to an uninsulated part of the reference potential setting line pattern, the conductive layer overlying at least a portion of said substrate and said circuit pattern between said plurality of IC pin lands and the pin insertion through-holes without contacting any of the IC pin lands.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-13 | 1999-05-15 | 1999-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-13 | 2003-05-15 | 2003-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-13 | 2007-05-15 | 2007-11-14 | $7700.00 | Window Closed / Lapsed |