Semiconductor device

Claim 2

A semiconductor device having a plurality of LSIs stacked in a semiconductor package, comprising: a package board; a first LSI connected to the package board and comprising a communication circuit performing data communication with the outside of the semiconductor package; a second LSI disposed above the first LSI and including a first storage device which has a plurality of first memory cells provided at intersection points of a plurality of first bit lines and a plurality of first word lines; a third LSI disposed above the second LSI and performing arithmetic processing by using information stored in the first storage device; and a first through silicon via penetrating the second LSI and electrically interconnecting the first, second, and third LSIs.

Claim 3

The semiconductor device according to claim 1 , wherein the first LSI writes first data received from a source outside the semiconductor package into the second LSI; and the third LSI reads the first data from the second LSI and performs the arithmetic processing on the first data.

Claim 4

The semiconductor device according to claim 1 , wherein: the third LSI writes second data resulting from the arithmetic processing into the second LSI; and the first LSI reads the second data from the second LSI and sends the second data to the outside of the semiconductor package.

Claim 5

The semiconductor device according to claim 1 , wherein the first through silicon via penetrates the first, second, and third LSIs.

Claim 6

The semiconductor device according to claim 1 , wherein the third LSI comprises a circuit performing the arithmetic processing disposed on the lower surface of the third LSI.

Claim 7

The semiconductor device according to claim 1 , wherein the first through silicon via penetrates the first and second LSIs; and the first LSI includes the communication circuit disposed on the lower surface of the first LSI.

Claim 8

The semiconductor device according to claim 1 , further comprising a first bonding wire interconnecting the package board and the third LSI, wherein: first electric power is supplied to the first, second, and third LSIs through the first through silicon via; and second electric power having a voltage different from the voltage of the first electric power is supplied to the third LSI through the first bonding wire.

Claim 9

The semiconductor device according to claim 7 , further comprising: a fourth LSI disposed between the second and third LSIs performing arithmetic processing using information stored in the first storage device; and a second through silicon via penetrating the fourth LSI and electrically interconnecting the third and fourth LSIs, but not the first and second LSIs; wherein the first electric power is supplied to the first, second, third, and fourth LSIs through the first through silicon via; and the second electric power having a voltage higher than the voltage of the first electric power is supplied to the third and fourth LSIs through the second through silicon via.

Claim 10

The semiconductor device according to claim 1 , further comprising: a fourth LSI disposed between the second and third LSIs and performing arithmetic processing by using information stored in the first storage device; and a second through silicon via penetrating the fourth LSI and electrically interconnecting the third and fourth LSIs, but not the first and second LSIs; wherein data communication among the first, second, third, and fourth LSIs is performed through the first through silicon via; and data communication between the third and fourth LSIs is performed through the second through silicon via.

Claim 11

The semiconductor device according to claim 1 , further comprising a second bonding wire electrically interconnecting the package board and the third LSI; wherein third data is communicated among the first, second, and third LSIs through the first through silicon via; and fourth data is communicated between the first and third LSIs through the second bonding wire.

Claim 12

The semiconductor device according to claim 10 , wherein the fourth data is identification information of the third LSI or information indicating an initial value of an operating frequency of the third LSI.

Claim 13

The semiconductor device according to claim 1 , wherein the first LSI further includes a first circuit block which, in an active state, outputs input data to the first through silicon via and, in an inactive state, places an output to the first through silicon via in a state independent of input data, and a first control block for controlling the first circuit block; the third LSI further includes a second circuit block which, in an active state, outputs input data to the first through silicon via and, in an inactive state, places an output to the first through silicon via in a state independent of input data, and a second control block for controlling the second circuit block; one of the first and second control blocks includes an arbitration function for determining which of the first and third LSIs should be granted access to the second LSI; if the first control block includes the arbitration function and grants the first LSI access to the second LSI, the first control block places the first circuit block in the active state; if the first control block includes the arbitration function and grants the third LSI access to the second LSI, the first control block places the first circuit block in the inactive state and sends a first signal indicating permission to use the first through silicon via to the second control block; and if the first control block does not includes the arbitration function, the first control block places the first circuit block in the active state when the first control block receives a second signal indicating permission to use the first through silicon via from the second control block, and places the first circuit block in the inactive state when the first control block does not receive the second signal from the second control block.

Claim 14

The semiconductor device according to claim 12 , wherein if the first LSI accesses the second LSI more frequently than the third LSI accesses the second LSI, the first control block includes the arbitration function; and if the third LSI accesses the second LSI more frequently than the first LSI accesses the second LSI, the second control block includes the arbitration function.

Claim 15

The semiconductor device according to claim 12 , wherein the first and second control blocks receive a specification signal indicating which of the first and second control blocks includes the arbitration function.

Claim 16

The semiconductor device according to claim 14 , wherein: the first LSI includes a first terminal for receiving the specification signal from a source outside the first LSI; and the third LSI includes a second terminal for receiving the specification signal from a source outside the third LSI.

Claim 17

The semiconductor device according to claim 12 , further comprising a nonvolatile memory storing an indication of which of the first and second control blocks includes the arbitration function.

Claim 18

The semiconductor device according to claim 1 , further comprising: a fifth LSI disposed between the first and second LSIs and comprising a second storage device including a plurality of memory cells provided at intersection points of a plurality of second bit lines and a plurality of second word lines; and a sixth LSI disposed between the second and third LSIs and performing arithmetic processing by using information stored in the first or second storage device; wherein the second LSI receives a first identification signal for distinguishing the second LSI from the fifth LSI; the fifth LSI receives a second identification signal for distinguishing the fifth LSI from the second LSI; the third LSI receives a third identification signal for distinguishing the third LSI from the fifth LSI; and the sixth LSI receives a fourth identification signal for distinguishing the sixth LSI from the third LSI.

Claim 19

The semiconductor device according to claim 17 , wherein the second LSI includes a first terminal receiving the first identification signal from a source outside the second LSI; the fifth LSI includes a second terminal receiving the second identification signal from a source outside the fifth LSI; the third LSI includes a third terminal receiving the third identification signal from a source outside the third LSI; and the sixth LSI includes a fourth terminal receiving the fourth identification signal from a source outside the sixth LSI.

Claim 20

The semiconductor device according to claim 17 further comprising a nonvolatile memory storing the first to fourth identification signals.

Claim 21

The semiconductor device according to claim 1 , wherein fifth data is communicated among the first, second, and third LSIs through the first through silicon via; and the fifth data includes first information indicating an LSI sending the fifth data and second information indicating an LSI to which the fifth data is to be sent.

Claim 22

The semiconductor device according to claim 1 , wherein the first LSI further includes a first wireless communication circuit; the third LSI further includes a second wireless communication circuit; and the first and second wireless communication circuits are used to perform data communication between the first LSI and the third LSI.

Claim 23

The semiconductor device according to claim 1 , further comprising a third through silicon via which is connected to a power-supply terminal of each of the first and third LSI, penetrates the second LSI, and is not connected to a power-supply terminal of the second LSI, wherein the first through silicon via supplies first electric power to the first, second, and third LSIs; and the third through silicon via supplies third electric power having a voltage different from the voltage of the first electric power to the third LSI.

Claim 24

The semiconductor device according to claim 1 , further comprising a fourth through silicon via which electrically interconnects the first and third LSIs, penetrates the second LSI, and is not connected to an input terminal of the first storage device, wherein communication between the first and third LSIs is performed through the fourth through silicon via.

Claim 25

The semiconductor device according to claim 1 , wherein the first through silicon via comprises: a first circuit disposed between the upper and lower surfaces of the first LSI for amplifying a signal in communication between the upper and lower surfaces of the first LSI, a second circuit disposed between the upper and lower surfaces of the second LSI for amplifying a signal in communication between the upper and lower surfaces of the second LSI, and a third circuit disposed between the upper and lower surfaces of the third LSI for amplifying a signal in communication between the upper and lower surfaces of the third LSI.