Patent US6940768B2 successfully refreshed from Google Patents.
US6940768B2
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US
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Programmable data strobe offset with DLL for double data rate (DDR) RAM memory
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2003-11-04
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Granted: 2005-09-06
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Expires: 2023-11-04
Abstract
Abstract A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or ‘eye’ of the read data window. However, in distinction from conventional techniques, the initial delay determined by the DLL is fine tuned with an offset determined by a memory test. Moreover, in an additional embodiment, the delay may be further adjusted during operation to compensate for environmental conditions by a PVT (process, value, temperature) circuit.
Inventors
- 👤 James A. Dahlberg
- 👤 Obed Duardo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C7/22; G11C7/222
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
67 words
A method of providing an optimal memory access strobe, comprising: determining an initial delay for a data access signal to a memory device by employing a delay locked loop (DLL) circuit to delay said data access signal to a center of a data window; performing a memory test of said memory device; and adjusting said initial delay by a fine tuning offset determined by said memory test.
Claim 2
Independent Claim
67 words
A method of providing an optimal memory access strobe, comprising: determining an initial delay for a data access signal to a memory device by employing a delay locked loop (DLL) circuit to delay said data access signal to a center of a data window; performing a memory test of said memory device; and adjusting said initial delay by a fine tuning offset determined by said memory test.
Claim 3
Dependent Claim
23 words
The method of providing an optimal memory access strobe according to claim 1 , wherein: said data access signal is a DQS strobe.
Claim 4
Dependent Claim
26 words
The method of providing an optimal memory access strobe according to claim 1 , wherein: said data access signal is a read data access clock signal.
Claim 5
Dependent Claim
26 words
The method of providing an optimal memory access strobe according to claim 1 , wherein: said data access signal is a write data access clock signal.
Claim 6
Dependent Claim
23 words
The method of providing an optimal memory access strobe according to claim 4 , wherein: said DQS strobe relates to a DDR-RAM device.
Claim 7
Dependent Claim
23 words
The method of providing an optimal memory access strobe according to claim 5 , wherein: said DQS strobe relates to a DDR-SDRAM device.
Claim 8
Dependent Claim
23 words
The method of providing an optimal memory access strobe according to claim 1 , wherein: said data window is a read data window.
Claim 9
Dependent Claim
23 words
The method of providing an optimal memory access strobe according to claim 1 , wherein: said data window is a write data window.
Claim 10
Dependent Claim
31 words
The method of providing an optimal memory access strobe according to claim 1 , further comprising: further adjusting said initial delay in correlation to actual environmental conditions using a PVT circuit.
Claim 11
Dependent Claim
72 words
Apparatus for providing an optimal memory access strobe, comprising: means for determining an initial delay for a data access signal to a memory device by employing a delay locked loop (DLL) circuit to delay said data access signal to a center of a data window; means for performing a memory test of said memory device; and means for adjusting said initial delay by a fine tuning offset determined by said memory test.
Claim 12
Dependent Claim
72 words
Apparatus for providing an optimal memory access strobe, comprising: means for determining an initial delay for a data access signal to a memory device by employing a delay locked loop (DLL) circuit to delay said data access signal to a center of a data window; means for performing a memory test of said memory device; and means for adjusting said initial delay by a fine tuning offset determined by said memory test.
Claim 13
Dependent Claim
23 words
The apparatus for providing an optimal memory access strobe according to claim 10 , wherein: said data access signal is a DQS strobe.
Claim 14
Dependent Claim
23 words
The apparatus for providing an optimal memory access strobe according to claim 11 , wherein: said DQS strobe relates to a DDR-RAM device.
Claim 15
Dependent Claim
23 words
The apparatus for providing an optimal memory access strobe according to claim 12 , wherein: said DQS strobe relates to a DDR-SDRAM device.
Claim 16
Dependent Claim
26 words
The apparatus for providing an optimal memory access strobe according to claim 10 , wherein: said data access signal is a read data access clock signal.
Claim 17
Dependent Claim
26 words
The apparatus for providing an optimal memory access strobe according to claim 10 , wherein: said data access signal is a write data access clock signal.
Claim 18
Dependent Claim
23 words
The apparatus for providing an optimal memory access strobe according to claim 10 , wherein: said data window is a read data window.
Claim 19
Dependent Claim
23 words
The apparatus for providing an optimal memory access strobe according to claim 10 , wherein: said data window is a write data window.
Claim 20
Dependent Claim
32 words
The apparatus for providing an optimal memory access strobe according to claim 10 , further comprising: PVT adjustment circuit means for further adjusting said initial delay in correlation to actual environmental conditions.
Claim 21
Dependent Claim
64 words
A DQS strobe controller for a double data rate (DDR) memory device, comprising: a delay line formed by a plurality of programmable delay elements to provide an initial delay; and an adder/subtracter element for implementing a fine tuning adjustment of said initial delay, said fine tuning adjustment being determined empirically by operation of said DQS strobe controller in operation with said DDR memory device.
Claim 22
Dependent Claim
64 words
A DQS strobe controller for a double data rate (DDR) memory device, comprising: a delay line formed by a plurality of programmable delay elements to provide an initial delay; and an adder/subtracter element for implementing a fine tuning adjustment of said initial delay, said fine tuning adjustment being determined empirically by operation of said DQS strobe controller in operation with said DDR memory device.
Claim 23
Dependent Claim
33 words
The DQS strobe controller for a double data rate (DDR) memory device according to claim 19 , further comprising: a PVT circuit to provide an additional fine tuning adjustment of said initial delay.
Claim 24
Dependent Claim
37 words
The DQS strobe controller for a double data rate (DDR) memory device according to claim 19 , wherein: said fine tuning adjustment is determined empirically by way of a memory test of said actual DDR memory device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-09-05 | 2009-03-07 | 2009-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-09-05 | 2013-03-07 | 2013-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-09-05 | 2017-03-07 | 2017-09-06 | $7700.00 | Window Closed / Lapsed |