Synchronous semiconductor memory device with a plurality of memory modules which has an additional function for masking a data strobe signal outputted from each memory module

Claim 2

A synchronous semiconductor memory device with a plurality of memory modules, the memory modules operating in synchronous with a clock signal, comprising: a chip set memory controller that controls a data input/output of the plurality of memory modules by outputting the clock signal; and a data strobe mask signal pin for receiving a data strobe mask signal, wherein in reading a data from the plurality of memory modules, the plurality of memory modules provides the chip set memory controller with a data strobe signal for strobing the data, and the chip set memory controller outputs a data mask signal for masking the data and an additional data strobe mask signal for masking the data strobe signal, to the plurality of memory modules.

Claim 3

The synchronous semiconductor memory device as set forth in claims 1 , wherein said each memory module includes a plurality of SDRAMs.

Claim 4

The synchronous semiconductor memory device as set forth in claims 1 , wherein said each memory module includes a plurality of DDR SDRAMs.

Claim 5

The synchronous semiconductor memory device as set forth in claim 3 , wherein said DDR SDRAM includes the data strobe mask signal pin for receiving the data strobe mask signal.

Claim 6

A synchronous semiconductor memory device comprising: a chip set memory controller having a data strobe mask function, first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, and a data strobe mask signal pin for receiving a data strobe mask signal, whereby the data inputted into each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data inputted into each memory module is controlled by a data strobe signal outputted from each memory module.

Claim 7

A synchronous semiconductor memory device comprising: a chip set memory controller having a data strobe mask function, first through N-th memory modules operated in synchronous with a clock signal outputted from the chip set memory controller, and a data strobe mask signal pin for receiving a data strobe mask signal, whereby the data inputted into each memory module are masked by a data mask signal outputted from the chip set memory controller, and the operation of the data inputted into each memory module is controlled by a data strobe signal outputted from each memory module.

Claim 8

The synchronous semiconductor memory device as set forth in claim 5 , wherein said chip set memory controller outputs the data strobe mask signal controlling the operation of the data strobe signal.

Claim 9

The synchronous semiconductor memory device as set forth in claims 5 , wherein said each memory module includes a plurality of SDRAMs.

Claim 10

The synchronous semiconductor memory device as set forth in claims 5 , wherein said each memory module includes a plurality of DDR SDRAMs.

Claim 11

The synchronous semiconductor memory device as set forth in claim 8 , wherein said DDR SDRAM includes the data strobe mask signal pin for receiving the data strobe mask signal.

Claim 12

A synchronous semiconductor memory device, comprising: first to N-th memory modules having a plurality of memory devices, and, a chip set memory controller for controlling the operations of the first to N-th memory modules, the chip set memory controller having a data strobe mask function, wherein the first through N-th memory modules operate in synchronous with a clock signal outputted from the chip set memory controller, wherein the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, wherein the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, wherein the chip set memory controller outputs a data strobe mask signal controlling the operation of the data strobe signal, and wherein each of the memory devices include a data strobe mask signal pin for receiving the data strobe mask signal; and wherein said each memory module includes a plurality of DDR SDRAMs.

Claim 13

A synchronous semiconductor memory device, comprising: first to N-th memory modules having a plurality of memory devices, and, a chip set memory controller for controlling the operations of the first to N-th memory modules, the chip set memory controller having a data strobe mask function, wherein the first through N-th memory modules operate in synchronous with a clock signal outputted from the chip set memory controller, wherein the data outputted from each memory module are masked by a data mask signal outputted from the chip set memory controller, wherein the operation of the data outputted from each memory module is controlled by a data strobe signal outputted from each memory module, wherein the chip set memory controller outputs a data strobe mask signal controlling the operation of the data strobe signal, and wherein each of the memory devices include a data strobe mask signal pin for receiving the data strobe mask signal; and wherein said each memory module includes a plurality of DDR SDRAMs.