US5587961A
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Synchronous memory allowing early read command in write to read transitions
Assignee: Round Rock Research LLC
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Filing: 1996-02-16
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Granted: 1996-12-24
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Expires: 2016-02-16
Abstract
Abstract A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.
Inventors
- 👤 Jeffrey P. Wright
- 👤 Hua Zheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
144 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a memory array having storage cells; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 2
Dependent Claim
144 words
A memory device responsive to command signals and operating in synchronization with active edges of a system clock, the memory device comprising: a memory array having storage cells; and a command decoder/controller responsive to selected command signals to initiate, at a first active edge of the system clock, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory array and to initiate, at a second active edge of the system clock, a read command controlling a read operation to transfer at least one output data set from the memory array, wherein one of the multiple input data sets transferred during the write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each input and output data set includes at least one bit of data.
Claim 3
Dependent Claim
40 words
The memory device of claim 1 further comprising a mode register for storing mode information, wherein the command controller is allowed to initiate the read command at the second active edge of the system clock based on the mode information.
Claim 4
Dependent Claim
46 words
The memory device of claim 2 wherein the mode information includes a read latency number, wherein when the read latency number is at least three clock cycles, the command controller is allowed to initiate the read command at the second active edge of the system clock.
Claim 5
Dependent Claim
45 words
The memory device of claim 3 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory device during the second system clock cycle is the last data set transferred during the write operation.
Claim 6
Dependent Claim
36 words
The memory device of claim 3 wherein when the read latency number is one or two clock cycles, the command controller is not allowed to initiate the read command until after the second system clock cycle.
Claim 7
Dependent Claim
12 words
The memory device of claim 2 wherein the mode register is programmable.
Claim 8
Dependent Claim
17 words
The memory device of claim 1 wherein the memory device is a synchronous dynamic random access memory.
Claim 9
Dependent Claim
17 words
The memory device of claim 1 wherein the memory device is a synchronous graphic random access memory.
Claim 10
Independent Claim
161 words
A method of initiating a read command in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals, a read command controlling a read operation to transfer at least one output data set from the memory device, wherein one of the multiple input data sets transferred during the write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 11
Independent Claim
161 words
A method of initiating a read command in a memory device responsive to command signals and operating in synchronization with active edges of a system clock, the method comprising the steps of: initiating, at a first active edge of the system clock, in response to selected command signals, a burst write command controlling a burst write operation to transfer multiple input data sets to the memory device, wherein each input data set includes at least one bit of input data; and initiating, at a second active edge of the system clock, in response to selected command signals, a read command controlling a read operation to transfer at least one output data set from the memory device, wherein one of the multiple input data sets transferred during the write operation is input into the memory device during a second system clock cycle beginning with the second active edge, and wherein each output data set includes at least one bit of output data.
Claim 12
Dependent Claim
41 words
The method of claim 9 further comprising the step of programming a mode register with mode information, wherein the step of initiating the read command at the second active edge of the system clock is performed based on the mode information.
Claim 13
Dependent Claim
44 words
The method of claim 10 wherein the mode information includes a read latency number, wherein the step of initiating the read command at the second active edge of the system clock is performed when the read latency number is at least three clock cycles.
Claim 14
Dependent Claim
44 words
The method of claim 11 wherein when the read latency number is three clock cycles, the one of the multiple input data sets input into the memory device during the second system clock cycle is the last data set transferred during the write operation.
Claim 15
Dependent Claim
34 words
The method of claim 11 wherein the step of initiating the read command is not performed until after the second system clock cycle when the read latency number is one or two clock cycles.
Claim 16
Dependent Claim
18 words
The method of claim 9 wherein the method is performed in a synchronous dynamic random access memory device.
Claim 17
Dependent Claim
18 words
The method of claim 9 wherein the method is performed in a synchronous graphic random access memory device.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |