Synchronous semiconductor device with memory chips in a module for controlling output of strobe signal for trigger in reading data

Claim 2

A synchronous semiconductor device comprising: a module; and a plurality of synchronous memory chips aligned in a sequential row in said module, for receiving external signals for control in synchronization with an external clock signal periodically supplied from the outside and performing a data transfer operation in synchronization with said external clock signal, wherein any two of said plurality of synchronous memory chips are defined as a first memory chip and a second memory chip, said first memory chip comprises means for stopping outputting data in response to a data mask signal for said first memory chip inhibiting said data transfer operation as one of said external signals, and said second memory chip comprises means for stopping outputting data in response to a data mask signal for said second memory chip inhibiting said data transfer operation as one of said external signals, and said second memory chip further comprises data output stop condition detecting means for detecting a shift from said data transfer operation of said first and second memory chips to a data output stop condition based on said data mask signal for said second memory chip and said data mask signal for said first memory chip.

Claim 3

The synchronous semiconductor device of claim 1, wherein said data output stop condition detecting means comprises activation detecting means for receiving said data mask signal for said first memory chip as a data mask control signal and detecting activation of both said data mask signal for said second memory chip and said data mask control signal in synchronization with said external clock signal as a shift to said data output stop condition, and said second memory chip further comprises strobe-signal generation means for activating a strobe signal for trigger before said data transfer operation to output said strobe signal to the outside and stopping outputting said strobe signal in accordance with a detection result of said activation detecting means.

Claim 4

The synchronous semiconductor device of claim 2, wherein said first and second memory chips are adjacent to each other.

Claim 5

The synchronous semiconductor device of claim 2, wherein said plurality of synchronous memory chips include a plurality of groups each consisting of said first and second memory chips.

Claim 6

The synchronous semiconductor device of claim 2, wherein at least one of said plurality of synchronous memory chips other than said first or second memory chip is defined as a third memory chip, said third memory chip comprises means for stopping outputting data in response to a data mask signal for said third memory chip, said activation detecting means comprises first activation detecting means for receiving said data mask signal for said first memory chip and said data mask signal for said third memory chip and detecting activation of all of said data mask signal for said second memory chip, said data mask signal for said third memory chip and said data mask control signal in synchronization with said external clock signal as a shift to said data output stop condition of said first and third memory chips, and said strobe-signal generation means comprises means for stopping outputting said strobe signal in accordance with a detection result of said first activation detecting means.

Claim 7

The synchronous semiconductor device of claim 1, wherein said first memory chip comprises means for generating a second data mask control signal which is activated in accordance with the activation timing of said data mask signal for said first memory chip and a first data mask control signal and outputting said second data mask control signal to said second memory chip, and said second memory chip comprises means for detecting activation of both said data mask signal for said second memory chip and said second data mask control signal in synchronization with said external clock signal as a shift to said data output stop condition, generating a data mask control signal which is activated in accordance with the detection timing and outputting said data mask control signal as said first data mask control signal to one of said plurality of synchronous memory chips other than said first or second memory chip.

Claim 8

The synchronous semiconductor device of claim 1, wherein the number of synchronous memory chips is n (n≧2), a first one of said plurality of synchronous memory chips receives a data mask signal therefor and a data mask control signal therefor which is always activated, and outputs a first signal which is in an activation level to a second one of said plurality of synchronous memory chips as said data mask control signal therefor only when both said data mask signal and said data mask control signal for said first one are activated in synchronization with said external clock signal, an i-th memory chip out of said second one to a (n-1)-th one of said plurality of synchronous memory chips outputs an i-th signal in said activation level to a (i+1)-th one of said plurality of synchronous memory chips as a data mask control signal for said (i+1)-th one only when both a data mask control signal for said i-th memory chip outputted from a (i-1)-th memory chip and a data mask signal for said i-th memory chip are activated in synchronization with said external clock signal, only an n-th one of said plurality of synchronous memory chips has a function of outputting a strobe signal for trigger which is activated before said data transfer operation to the outside, and said n-th memory chip stops outputting said strobe signal only when both said data mask control signal for said n-th memory chip outputted from a (n-1)-th one of said plurality of synchronous memory chips and a data mask signal for said n-th memory chip are activated in synchronization with said external clock signal.

Claim 9

The synchronous semiconductor device of claim 1, wherein each of said plurality of synchronous memory chips receives said external signals and performs said data transfer operation in synchronization with a rising edge and a falling edge of said external clock signal, respectively.

Claim 10

The synchronous semiconductor device of claim 1, wherein each of said plurality of synchronous memory chips comprises means for generating an internal clock signal obtained by multiplying said external clock signal by two, and each of said plurality of synchronous memory chips receives said external signals and performs said data transfer operation in synchronization with each edge of said internal clock signal.

Claim 11

The synchronous semiconductor device of claim 1, wherein each of said plurality of synchronous memory chips comprises means for generating an internal clock signal which is activated in synchronization with a rising edge of said external clock signal and a timing at which a duty of said external clock signal becomes 50%, and each of said plurality of synchronous memory chips receives said external signals and performs said data transfer operation in synchronization with each edge of said internal clock signal.

Claim 12

A synchronous semiconductor device, comprising: a module; and a plurality of synchronous memory chips aligned in a sequential row in said module, for receiving external signals for control in synchronization with an external clock signal periodically supplied from an outside and performing a data transfer operation in synchronization with said external clock signal, wherein said plurality of synchronous memory chips are divided into a plurality of groups each consisting of first and second memory chips, said second memory chip activates a strobe signal for trigger before said data transfer operation and outputs said strobe signal to said outside, and said second memory chip has a function of receiving a data mask signal for said first memory chip as a data mask control signal and a data mask signal for said second memory chip and of stopping outputting said strobe signal only when both said data mask signal for said second memory chip and said data mask control signal are activated in synchronization with said external clock signal.

Claim 13

A synchronous semiconductor device, comprising: a module; and a plurality of synchronous memory chips aligned in a sequential row in said module, for receiving external signals for control in synchronization with an external clock signal periodically supplied from an outside and performing a data transfer operation in synchronization with said external clock signal, wherein said plurality of synchronous memory chips are divided into a plurality of groups each consisting of first and second memory chips, said second memory chip activates a strobe signal for trigger before said data transfer operation and outputs said strobe signal to said outside, and said second memory chip has a function of receiving a data mask signal for said first memory chip as a data mask control signal and a data mask signal for said second memory chip and of stopping outputting said strobe signal only when both said data mask signal for said second memory chip and said data mask control signal are activated in synchronization with said external clock signal.

Claim 14

The synchronous semiconductor device of claim 11, wherein each of said first and second memory chips further comprises a portion for stopping outputting data in accordance with an activation timing of said corresponding data mask signal.