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US5696732A Expired / Lapsed US ⏱️ 0.0 years remaining

Burst EDO memory device

Assignee: Round Rock Research LLC
•
Filing: 1996-11-21
•
Granted: 1997-12-09
•
Expires: 2016-11-21
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Abstract

Abstract An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Inventors

  • 👤 Paul S. Zagar
  • 👤 Brett L. Williams

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 02:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1039; G11C7/1045; G11C7/1096; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 223 words
A method of accessing a further memory element of a memory device, the memory device having an array of memory elements, where one of the elements has been identified and accessed, the memory device includes an address latch, an address counter, an address strobe node for receiving a column address strobe, and an output data, the method comprising: providing the address of the further element from within the memory device and accessing the further element, in response to a transition of an address latch signal the step of providing the address further comprising the sub-steps of: applying a first column address strobe to the address strobe node for latching a first column address; accessing a first memory element of the array of memory elements at the first column address; applying a second column address strobe to the address strobe node for advancing the column address within the memory device to specify a second column address; accessing a second memory element of the array of memory elements at the second column address; switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.
Claim 2
Independent Claim 223 words
A method of accessing a further memory element of a memory device, the memory device having an array of memory elements, where one of the elements has been identified and accessed, the memory device includes an address latch, an address counter, an address strobe node for receiving a column address strobe, and an output data, the method comprising: providing the address of the further element from within the memory device and accessing the further element, in response to a transition of an address latch signal the step of providing the address further comprising the sub-steps of: applying a first column address strobe to the address strobe node for latching a first column address; accessing a first memory element of the array of memory elements at the first column address; applying a second column address strobe to the address strobe node for advancing the column address within the memory device to specify a second column address; accessing a second memory element of the array of memory elements at the second column address; switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.
Claim 3
Dependent Claim 27 words
The method of claim 1, further comprising: driving data from the one element of the memory device after a plurality of transitions of the address latch signal.
Claim 4
Dependent Claim 53 words
The method of claim 1, further comprising the steps of: applying a third column address strobe to the address strobe node for advancing the column address to specify a third column address; and latching an output of the memory device from the first column address in synchronization with the third column address strobe.
Claim 5
Dependent Claim 29 words
The method of claim 3, further comprising the step of: selecting a burst mode of operation of the memory device prior to said applying the first column address strobe.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-12-08 2001-06-09 2001-12-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-12-08 2005-06-09 2005-12-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-12-08 2009-06-09 2009-12-09 $7700.00 Window Closed / Lapsed

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