Semiconductor memory device incorporating address change detection circuit for page mode access

Claim 2

A semiconductor memory device capable of operating in a normal access mode and a rapid access mode, the semiconductor memory device comprising: change detection means, connected to a predetermined number of high-order bits of an address signal, for detecting a change of the address signal; timer means connected to the change detection means for, when the change detection means detects the change of the address signal, generating a change indicative signal having a specific time width, the change indicative signal indicating occurrence of the change of the address signal; and output means connected to the timer means for outputting a miss signal based on the change indicative signal generated by the timer means, the miss signal controlling a waiting operation of access of an external apparatus in each of the access modes.

Claim 3

A semiconductor memory device according to claim 1, wherein the change detection means includes: a plurality of first delay circuits, each of which receiving one of the predetermined number of the high-order bits of the address signal as an input bit signal and producing a delayed bit signal by delaying the input bit signal by a first predetermined delay time period; and a plurality of comparison means each for comparing the input bit signal with the delayed bit signal.

Claim 4

A semiconductor memory device according to claim 1, wherein the rapid access mode is a page mode.

Claim 5

A semiconductor memory device according to claim 2, wherein the timer means comprises: a second delay circuit; a plurality of n-channel MOS transistors each having a source terminal grounded, a drain terminal connected to an input of the second delay circuit, and a gate terminal connected to each of the comparison means; and a p-channel MOS transistor connected to the input of the second delay circuit and a power source.

Claim 6

A semiconductor memory device according to claim 2, wherein the output means comprises: a third delay circuit for delaying the change indicative signal by a second predetermined delay time period; a NAND circuit for comparing the change indicative signal as generated by the timer means with the delayed change indicative signal; and an inverter circuit for outputting the miss signal based on an output signal of the NAND circuit.

Claim 7

A semiconductor memory device according to claim 5, wherein the third delay circuit includes a plurality of inverters.

Claim 8

A semiconductor memory device according to claim 6, wherein the plurality of inverters are an even number of inverters.

Claim 9

A semiconductor memory device according to claim 2, wherein the specific time width of the change indicative signal is determined based on the first predetermined delay time period

Claim 10

A semiconductor memory device according to claim 1, wherein the miss signal is produced in an asynchronous manner.

Claim 11

A semiconductor memory device capable of operating in a normal access mode and a rapid access mode, the semiconductor memory device comprising an address change detection circuit for receiving a predetermined number of high-order bits of an address signal, detecting a change of the address signal and outputting a miss signal indicative of occurrence of the change of the address signal, wherein the address change detection circuit comprises: a plurality of first delay circuits, each of which receiving one of the predetermined number of the high-order bits of the address signal as an input bit signal and producing a delayed bit signal by delaying the input bit signal by a first predetermined delay time period; a plurality of comparison circuits, connected to the plurality of first delay circuits, each for comparing the input bit signal with the delayed bit signal and outputting a first signal indicative of a result of the comparison; a judging circuit, connected to the plurality of comparison circuits, for receiving the respective first signals which are output from each of the comparison circuits and generating a second signal having a specific time width, the second signal indicating occurrence of a difference between the input bit signal and the delayed bit signal in at least one of the predetermined high-order bits of the address signal, thereby indicating occurrence of the change of the address signal; and an output circuit, connected to the judging circuit, for generating the miss signal in accordance with the second signal, the miss signal controlling a waiting operation of access of an external apparatus in each of the access modes.

Claim 12

A semiconductor memory device capable of operating in a normal access mode and a rapid access mode, the semiconductor memory device comprising an address change detection circuit for receiving a predetermined number of high-order bits of an address signal, detecting a change of the address signal and outputting a miss signal indicative of occurrence of the change of the address signal, wherein the address change detection circuit comprises: a plurality of first delay circuits, each of which receiving one of the predetermined number of the high-order bits of the address signal as an input bit signal and producing a delayed bit signal by delaying the input bit signal by a first predetermined delay time period; a plurality of comparison circuits, connected to the plurality of first delay circuits, each for comparing the input bit signal with the delayed bit signal and outputting a first signal indicative of a result of the comparison; a judging circuit, connected to the plurality of comparison circuits, for receiving the respective first signals which are output from each of the comparison circuits and generating a second signal having a specific time width, the second signal indicating occurrence of a difference between the input bit signal and the delayed bit signal in at least one of the predetermined high-order bits of the address signal, thereby indicating occurrence of the change of the address signal; and an output circuit, connected to the judging circuit, for generating the miss signal in accordance with the second signal, the miss signal controlling a waiting operation of access of an external apparatus in each of the access modes.

Claim 13

A semiconductor memory device according to claim 10, wherein the rapid access mode is a page mode.

Claim 14

A semiconductor memory device according to claim 10, wherein each of the first delay circuits includes a plurality of inverters.

Claim 15

A semiconductor memory device according to claim 12, wherein the plurality of inverters are an even number of inverters connected with each other in series.

Claim 16

A semiconductor memory device according to claim 10, wherein each of the comparison circuits includes an exclusive-OR circuit.

Claim 17

A semiconductor memory device according to claim 10, wherein the judging circuit comprises: a second delay circuit; a plurality of n-channel MOS transistors each having a source terminal grounded, a drain terminal connected to an input of the second delay circuit, and a gate terminal connected to each of the comparison circuits; and a p-channel MOS transistor connected to the input of the second delay circuit and a power source.

Claim 18

A semiconductor memory device according to claim 10, wherein the output circuit comprises: a third delay circuit for delaying the second signal by a second predetermined delay time period; a NAND circuit for comparing the second signal as generated by the judging circuit with the delayed second signal; and an inverter circuit for outputting the miss signal based on an output signal of the NAND circuit.

Claim 19

A semiconductor memory device according to claim 16, wherein the third delay circuit includes a plurality of inverters.

Claim 20

A semiconductor memory device according to claim 17, wherein the plurality of inverters are a second even number of inverters.

Claim 21

A semiconductor memory device according to claim 10, wherein the output circuit comprises: a third delay circuit for delaying the second signal by a second predetermined delay time period; a NAND circuit for comparing the second signal as generated by the judging circuit with the delayed second signal; and an inverter circuit for outputting the miss signal based on an output signal of the NAND circuit; wherein each of the first delay circuits includes a first even number of inverters connected with each other in series, and the third delay circuit includes a second even number of inverters connected with each other in series.

Claim 22

A semiconductor memory device according to claim 19, wherein the first even number is equal to the second even number, whereby a time period of the miss signal is twice as long as the first predetermined delay time period.

Claim 23

A semiconductor memory device according to claim 10, wherein the specific time width of the second signal is determined based on the first predetermined delay time period.

Claim 24

A semiconductor memory device according to claim 10, wherein the miss signal is generated in an asynchronous manner.