US4922122A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for the detection of address transitions
Assignee: STMicroelectronics SA
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Filing: 1988-08-23
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Granted: 1990-05-01
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Expires: 2008-08-23
Abstract
Abstract A circuit for the detection of address transistions in an integrated circuit comprises a logic signal input terminal, a D flip-flop for memorizing the state of the input signal, and a comparator having a first input terminal connected to the logic signal input terminal and a second input terminal connected to the output terminal of the memorizing means. The comparator gives a first logic level when its input terminals receive a same logic signal level and a second logic signal level when its input terminals receive different logic signal levels. This circuit enables the generation of an output pulse as soon as there is an input address transition, in such a way that the time delay of the output with respect to the address transition is kept to a minimum and the duration of the pulse is suitable for use in the integrated circuit which is sought to be activated.
Inventors
- 👤 Bruno Dubujet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:48
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
133 words
A circuit for the detection of address transitions in an integrated circuit wherein an output pulse is generated as soon as there is an address change at an input terminal, said detection circuit comprising: an input terminal to which is applied an input logic signal, means connected to the input terminal for memorizing the state of the input logic signal and providing an output signal, comparison means having a first input terminal connected to the logic signal input terminal and a second input terminal connected to the output terminal of the memorizing means, said comparison means having an output terminal which is at a first logic signal level when its input terminals receive the same logic signal levels and at a second logic signal level when its input terminals receive different logic levels.
Claim 2
Dependent Claim
133 words
A circuit for the detection of address transitions in an integrated circuit wherein an output pulse is generated as soon as there is an address change at an input terminal, said detection circuit comprising: an input terminal to which is applied an input logic signal, means connected to the input terminal for memorizing the state of the input logic signal and providing an output signal, comparison means having a first input terminal connected to the logic signal input terminal and a second input terminal connected to the output terminal of the memorizing means, said comparison means having an output terminal which is at a first logic signal level when its input terminals receive the same logic signal levels and at a second logic signal level when its input terminals receive different logic levels.
Claim 3
Dependent Claim
49 words
A circuit for the detection of address transitions according to claim 1 wherein said comparison means is an exclusive-OR gate having a first input terminal to which is applied said input logic signal and a second input terminal to which is applied said output signal of said memorizing means.
Claim 4
Dependent Claim
49 words
A circuit for the detection of address transitions according to claim 1 wherein said comparison means is an exclusive-NOR gate having a first input terminal to which is applied said input logic signal and a second input terminal to which is applied said output signal of said memorizing means.
Claim 5
Dependent Claim
57 words
A circuit for the detection of address transitions according to claim 1, wherein said memorizing means is a D flip-flop circuit having a first input terminal to which is applied said input logic signal and a second input terminal corresponding to a clock signal input terminal which is connected to the output terminal of said comparison means.
Claim 6
Dependent Claim
57 words
A circuit for the detection of address transitions according to claim 1, wherein said memorizing means is a D flip-flop having a first input terminal to which is applied said input logic signal and a second input terminal corresponding to the inverse clock signal input terminal which is connected to the output terminal of said comparison means.
Claim 7
Dependent Claim
159 words
A circuit for the detection of address transitions, wherein an output pulse is generated as soon as there is an address change at an input terminal, said detection circuit comprising: an input terminal to which is applied an input logic signal, means for memorizing the state of the input logic signal, said means having a first input connected to said input terminal, an enabling input for receiving an enabling signal, whereby the state of the input signal is stored in the memorizing means upon reception of the enabling signal, and an output for supplying a memorized logic signal, a comparison circuit for comparing the signal on the input terminal and the memorized logic signal, said comparison circuit providing an output signal depending upon whether the input signal and the memorized signal have the same logic level or not, said output signal of the comparison circuit being supplied as an enabling signal to the enabling input of the memorizing circuit.
Claim 8
Dependent Claim
159 words
A circuit for the detection of address transitions, wherein an output pulse is generated as soon as there is an address change at an input terminal, said detection circuit comprising: an input terminal to which is applied an input logic signal, means for memorizing the state of the input logic signal, said means having a first input connected to said input terminal, an enabling input for receiving an enabling signal, whereby the state of the input signal is stored in the memorizing means upon reception of the enabling signal, and an output for supplying a memorized logic signal, a comparison circuit for comparing the signal on the input terminal and the memorized logic signal, said comparison circuit providing an output signal depending upon whether the input signal and the memorized signal have the same logic level or not, said output signal of the comparison circuit being supplied as an enabling signal to the enabling input of the memorizing circuit.
Claim 9
Dependent Claim
33 words
A circuit according to claim 6, wherein said comparison circuit comprises an exclusive-OR gate having one input connected to said input terminal and another input connected to the output of the memorizing means.
Claim 10
Dependent Claim
14 words
A circuit according to claim 6, wherein said comparison circuit is an exclusive-NOR gate.
Claim 11
Dependent Claim
44 words
A circuit according to one of claims 6, 7, or 8, wherein said memorizing means is a flip-flop of the D flip-flop type, having a D input connected to the input terminal and a clock input connected to the output of the comparison circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |