MOS Transition detector for plural signal lines using non-overlapping complementary interrogation pulses

Claim 1

Insulated-gate field-effect transistor integrated circuit for delivering a digital signal (a) at the application of an interrogation pulse (as) if a change of state has occurred in a one-out-of-n system until the instant of interrogation, characterized by the following features: each signal (1 . . . n) of the one-out-of-n system is applied via the channel of a first transistor (t1) to the input of a first inverter (i1) and to the gate of a second transistor (t2) whose channel is grounded at one end, while the other end is connected via the channel of a third transistor (t3) to a load device (l) common to all signals (1 . . . n) and connected to a supply-voltage source (u); the output of the first inverter (i1) is connected to the input of a second inverter (i2) and, via the channel of a fourth transistor (t4), to the gate of the third transistor (t3); the input of the first inverter (i1) is connected to the output of the second inverter (i2) via the channel of a fifth transistor (t5); the interrogation pulses (as) are applied to a pulse shaper (if) which produces two nonoverlapping clock signals (f, f) therefrom; the first clock signal (f) is applied to the gates of the fourth and fifth transistors (t4, t5), and the second clock signal (f) is applied to the gate of the first transistor (t1).