Quadrature tach decoder circuit

Claim 2

Circuit for detecting movement of a member, comprising: tach means for supplying two quadrature tach pulses in response to member movement; gate means for receiving said tach pulses and generating tach sequence pulses indicative of which tach phase is leading, and a multiple tach frequency clock; logic means for generating a logic state change having a first input coupled to receive said tach sequence pulses and a second input coupled to receive said clock, said first input of said logic means being in a first logic state when said clock occurs to indicate a first direction of member movement and being in a second logic state when said clock occurs to indicate a second direction; and means external to said gate and logic means for delaying said multiple frequency clock so that a reference edge thereof always occurs after said logic state change generated by said logic means.

Claim 3

The circuit of claim 1 wherein the gate means further includes: a first exclusive OR gate for comparing the two quadrature tach pulses; a first gate/delay means coupled to a first of the tach pulses for generating a short duration pulse; and a second exclusive OR gate coupled to the first exclusive OR gate and to the first gate/delay means for generating the tach sequence pulses; said first input of the logic means being coupled to the second exclusive OR gate to generate the logic state indicative of the tach sequence in response to the clock.

Claim 4

The circuit of claim 2 wherein: said gate means further includes a second gate/delay means is coupled to an output of the first exclusive OR gate; and said second input of the logic means is clocked by an output of said second gate/delay means.

Claim 5

A circuit for decoding quadrature tach pulses, comprising: first exclusive OR gate means for comparing the tach pulses and for generating 2-times tach frequency pulses; first means including a delay coupled to receive one of said tach pulses for generating a narrow pulse at each of the tach pulse edges; second exclusive OR gate means coupled to receive the 2-times tach pulses and the narrow pulses for generating tach sequence pulses; second means including a delay coupled to the first exclusive OR gate means for generating 4-times tach frequency pulses; bistable logic means coupled to the second exclusive OR gate means for generating a selected logic state in response to the 4-times tach pulses; and means for delaying said 4-times tach frequency pulses so that a reference edge thereof always occurs after a change in the logic state of the bistable logic means.

Claim 6

A circuit for decoding quadrature tach pulses, comprising: first exclusive OR gate means for comparing the tach pulses and for generating 2-times tach frequency pulses; first means including a delay coupled to receive one of said tach pulses for generating a narrow pulse at each of the tach pulse edges; second exclusive OR gate means coupled to receive the 2-times tach pulses and the narrow pulses for generating tach sequence pulses; second means including a delay coupled to the first exclusive OR gate means for generating 4-times tach frequency pulses; bistable logic means coupled to the second exclusive OR gate means for generating a selected logic state in response to the 4-times tach pulses; and means for delaying said 4-times tach frequency pulses so that a reference edge thereof always occurs after a change in the logic state of the bistable logic means.

Claim 7

The circuit of claim 1 wherein the gate means further includes: a first exclusive OR gate for comparing the two quadrature tach pulses; a bistable logic means having a first input coupled to receive and delay a second one of said tach pulses and having a second input for receiving said multiple tach frequency clock; and a second exclusive OR gate for comparing a first and said delayed second tach pulses for generating the tach sequence pulses.

Claim 8

The circuit of claim 5 wherein the gate means further include: a gate/delay means coupled to an output of the first exclusive OR gate and having an output providing said multiple tach frequency clock.

Claim 9

A circuit for decoding quadrature tach pulses, comprising: first exclusive OR gate means for receiving and comparing the tach pulses and for generating 2-times tach frequency pulses; means including a delay coupled to an output of the first exclusive OR gate means for generating a 4-times tach frequency pulses; a first bistable logic means having a first input coupled to receive and delay a second one of said tach pulses and having a clock input for receiving said 4-times tach frequency pulses; a second exclusive OR gate coupled to compare a first and said delayed second tach pulses and to generate tach sequence pulses; a second bistable logic means having a first input coupled to an output of said second exclusive OR gate for generating a selected logic state in response to the 4-times tach frequency pulses; and means for delaying said 4-times tach frequency pulses so that a reference edge thereof always occurs after a change in the logic state of the second bistable logic means.

Claim 10

A circuit for decoding quadrature tach pulses, comprising: first exclusive OR gate means for receiving and comparing the tach pulses and for generating 2-times tach frequency pulses; means including a delay coupled to an output of the first exclusive OR gate means for generating a 4-times tach frequency pulses; a first bistable logic means having a first input coupled to receive and delay a second one of said tach pulses and having a clock input for receiving said 4-times tach frequency pulses; a second exclusive OR gate coupled to compare a first and said delayed second tach pulses and to generate tach sequence pulses; a second bistable logic means having a first input coupled to an output of said second exclusive OR gate for generating a selected logic state in response to the 4-times tach frequency pulses; and means for delaying said 4-times tach frequency pulses so that a reference edge thereof always occurs after a change in the logic state of the second bistable logic means.