US4337435A
Expired / Lapsed
US
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Digital phase sequence detector
Assignee: ABB Inc USA
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Filing: 1980-06-10
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Granted: 1982-06-29
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Expires: 2000-06-10
Abstract
Abstract A digital phase sequence detector which operates completely independent of signal amplitude values to provide an output signal having a logic level indicative of which of two phasors being compared is leading. The detector develops first and second feedback signals which determine the stable state of the circuit. This feedback arrangement enables the detector to be constructed of standard integrated circuits devoid of flip-flops or other memory elements requiring a clock. The level of the output signal of the detector persists for as long as the relationship being indicated persists, eliminating the need for pulse stretchers, timers, or the like.
Inventors
- 👤 Joseph P. Munoz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:47
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/38; H02H3/382; G; G01; G01R; G01R29/00; G01R29/18; G01R25/00; G01R25/005; H03; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
282 words
A digital phase sequence detector, constructed of standard logic gates devoid of memory elements, which detects phase sequence between first and second phasors, providing a change in its output as the first and second phasors exchange lead and lag positions, which change persists as long as the new relationship persists, comprising: means providing a first phasor, means squaring the waveform of aid first phasor to provide a signal V P , and its complement V P , means providing a second phasor, means squaring the waveform of said second phasor to provide a signal V O , and its complement V O , first logic means providing a first feedback signal Y 1 , and its complement Y 1 , second logic means providing a second feedback Y 2 , and its complement Y 2 , said first logic means being responsive to signals V O , V P and Y 1 such that the first feedback signal Y 1 is equal to (V.sub.O V.sub.P)(V.sub.P Y.sub.1)(V.sub.O Y.sub.1), said second logic means being responsive to signals V O , V P and Y 2 such that the second feedback signal Y 2 is equal to (V.sub.O V.sub.P)(V.sub.P Y.sub.2)(V.sub.O Y.sub.2), and third logic means providing an output signal having a first logic level when signal V O leads signal V P and a second logic level when signal V O lags signal V P , said third logic means being responsive to signals V O , V O , V P , V P , Y 1 , Y 1 , Y 2 and Y 2 , such that its output signal is equal to (V.sub.O Y.sub.1 Y.sub.2)(V.sub.P Y.sub.2 Y.sub.1)(V.sub.O Y.sub.1 Y.sub.2)(V.sub.P Y.sub.1 Y.sub.2).
Claim 2
Dependent Claim
282 words
A digital phase sequence detector, constructed of standard logic gates devoid of memory elements, which detects phase sequence between first and second phasors, providing a change in its output as the first and second phasors exchange lead and lag positions, which change persists as long as the new relationship persists, comprising: means providing a first phasor, means squaring the waveform of aid first phasor to provide a signal V P , and its complement V P , means providing a second phasor, means squaring the waveform of said second phasor to provide a signal V O , and its complement V O , first logic means providing a first feedback signal Y 1 , and its complement Y 1 , second logic means providing a second feedback Y 2 , and its complement Y 2 , said first logic means being responsive to signals V O , V P and Y 1 such that the first feedback signal Y 1 is equal to (V.sub.O V.sub.P)(V.sub.P Y.sub.1)(V.sub.O Y.sub.1), said second logic means being responsive to signals V O , V P and Y 2 such that the second feedback signal Y 2 is equal to (V.sub.O V.sub.P)(V.sub.P Y.sub.2)(V.sub.O Y.sub.2), and third logic means providing an output signal having a first logic level when signal V O leads signal V P and a second logic level when signal V O lags signal V P , said third logic means being responsive to signals V O , V O , V P , V P , Y 1 , Y 1 , Y 2 and Y 2 , such that its output signal is equal to (V.sub.O Y.sub.1 Y.sub.2)(V.sub.P Y.sub.2 Y.sub.1)(V.sub.O Y.sub.1 Y.sub.2)(V.sub.P Y.sub.1 Y.sub.2).
Claim 3
Dependent Claim
23 words
The digital phase detector of claim 1, wherein the first, second and third logic means are constructed entirely of NAND and NOT gates.
Claim 4
Dependent Claim
64 words
The digital phase detector of claim 1 including fourth logic means responsive to the output signal of the third logic means and to signal V P , with the output of said fourth logic means being responsive to the output signal of said third logic means as long as signal V P is present, and otherwise providing a signal having a predetermined logic level.
Claim 5
Dependent Claim
84 words
The digital phase detector of claim 3 including means responsive to signal V P providing a signal V PP in response to the positive half cycle of signal V P and a signal V PN responsive to the negative half cycle of signal V P , with the forth logic means being responsive to both signals V PP and V PN , providing a signal having the predetermined logic level in response to the loss of either signal V PP or V PN .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-28 | 1985-12-28 | 1986-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-28 | 1989-12-28 | 1990-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-28 | 1993-12-28 | 1994-06-29 | $7700.00 | Window Closed / Lapsed |