US3986128A
Expired / Lapsed
US
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Phase selective device
Assignee: ABB Norden Holding AB
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Filing: 1975-08-14
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Granted: 1976-10-12
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Expires: 1995-08-14
Abstract
Abstract An arrangement for determining the phase position between two signals includes a circuit containing a gate with two inputs for the signals and an output for a first output signal which is dependent on the phase position between the input signals. A flip-flop has an input for one of the input signals and a second input for the first output signal. The second input of the flip-flop contains a time-delay circuit for the first output signal. Two similar circuits can be used.
Inventors
- 👤 Leif Eriksson
- 👤 Lennart Thornell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:41
CPC Classifications
G; G01; G01R; G01R25/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
110 words
Device for determining the phase position between two signals (1,3), comprising at least one circuit which contains a gate (11,11') with at least two inputs (12,13;12',13') for said signals (1,2,3,4) and an output (14,14') for a first output signal (5,6) which is dependent on the phase position between the input signals, and a flip-flop (15,15') having a first input (19,19') for one of the input signals (3,4) or a complement signal thereof and a second input (18,18') for said first output signal (5,6), the connection between the gate (11,11') and the second input (18,18') of the flip-flop (15,15') containing a time delay circuit (24,24') for said first output signal (5,6).
Claim 2
Dependent Claim
110 words
Device for determining the phase position between two signals (1,3), comprising at least one circuit which contains a gate (11,11') with at least two inputs (12,13;12',13') for said signals (1,2,3,4) and an output (14,14') for a first output signal (5,6) which is dependent on the phase position between the input signals, and a flip-flop (15,15') having a first input (19,19') for one of the input signals (3,4) or a complement signal thereof and a second input (18,18') for said first output signal (5,6), the connection between the gate (11,11') and the second input (18,18') of the flip-flop (15,15') containing a time delay circuit (24,24') for said first output signal (5,6).
Claim 3
Dependent Claim
20 words
Device according to claim 1, in which the time delay circuit (24,24') contains a capacitor (25,25') as a delay element.
Claim 4
Dependent Claim
64 words
Device according to claim 1, which comprises a first and a second circuit, the second circuit being fed with the inverted input signals of the first circuit and a NAND gate (26) with two inputs having one of its inputs (27) connected to the output (23) of the first circuit and its other input (28) connected to the output (23') of the second circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-12 | 1980-04-12 | 1980-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-12 | 1984-04-12 | 1984-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-12 | 1988-04-12 | 1988-10-12 | $7700.00 | Window Closed / Lapsed |