Circuit for producing an output signal pulse of a width equal to the period between separated input signal pulse pairs

Claim 2

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which complementary logic output signals are present upon said Q and Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof from said initial first state to a second state in which the said complementary logic output signals present upon said Q and Q output terminals are reversed; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first circuit means for producing an output signal pulse of a width equal to the period between the pulses of each oF said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second circuit means for producing a reset signal; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 3

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal puse applied to the said clock pulse input terminal thereof from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second circuit means for producing a reset signal; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 4

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal puse applied to the said clock pulse input terminal thereof from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second circuit means for producing a reset signal; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 5

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second circuit means for producing a reset signal when said output signal of one of said first and second circuit means is a logic 0; and means for aPplying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 6

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second circuit means for producing a reset signal when said output signal of one of said first and second circuit means is a logic 0; and means for aPplying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 7

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof; from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first gate circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second gate circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second gate circuit means for producing a reset signal; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 8

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof; from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first gate circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second gate circuit means for producing an output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second gate circuit means for producing a reset signal; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 9

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting sAid Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof; from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first NAND gate circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second NAND gate circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second NAND gate circuit means for producing a reset signal when said output signal of one of said first and second circuit means is a logic 0; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 10

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals, initially in a first state in which a logic 0 output signal is present upon said Q output terminals and a logic 1 output signal is present upon said Q output terminals; means for electrically interconnecting sAid Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits whereby each may be triggered by a signal pulse applied to the said clock pulse input terminal thereof; from said initial first state to a second state in which a logic 1 output signal is present upon said Q output terminal and a logic 0 output signal is present upon said Q output terminal; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits for triggering said J-K flip-flop circuit to said second state; first NAND gate circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when one pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said one pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by the other pulse of each of said input signal pulse pairs; second NAND gate circuit means for producing a logic 0 output signal pulse of a width equal to the period between the pulses of each of said separated input signal pulse pairs when the other pulse of each of said input signal pulse pairs is the first occurring in response to the logic 1 output signal upon said Q output terminal of the one of said J-K flip-flop circuits triggered to said second state by said other pulse of each of said input signal pulse pairs and to the logic 1 output signal upon said Q output terminal of the other one of said J-K flip-flop circuits while in the said initial first state until triggered to said second state by said one pulse of each of said input signal pulse pairs; reset circuit means responsive to said output signals of said first and second NAND gate circuit means for producing a reset signal when said output signal of one of said first and second circuit means is a logic 0; and means for applying said reset signal to said reset input terminal of both said first and second J-K flip-flop circuits for resetting both of said J-K flip-flop circuits to said initial first state.

Claim 11

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits; first, second and third NAND gate circuits each having two input and an output terminals; means for connecting said Q output terminal of one of said J-K flip-flop circuits and said Q output terminal of the otHer one of said J-K flip-flop circuits to respective said input terminals of said first of said NAND gate circuits; means for connecting said Q output terminal of said other one of said J-K flip-flop circuits and said Q output terminal of said one of said J-K flip-flop circuits to respective input terminals of said second of said NAND gate circuits; means for connecting said output terminal of each of said first and second NAND gate circuits to respective said input terminals of said third of said NAND gate circuits; output circuit means through which said output terminal of each of said first and second NAND gate circuits may be connected to external circuitry; first and second monostable multivibrator circuits each having an input and an output terminals; means for connecting said output terminal of said third NAND gate circuit to said input terminal of one of said monostable multivibrator circuits; means for connecting said output terminal of said one of said monostable multivibrator circuits to said input terminal of the other one of said monostable multivibrator circuits; and means for connecting said output terminal of said other one of said monostable multivibrator circuits to said reset input terminal of both of said first and second J-K flip-flop circuits.

Claim 12

A circuit for producing an output signal pulse of a width equal to the period between the pulses of separated input signal pulse pairs comprising: first and second J-K flip-flop circuits, each having J and K input terminals, a clock pulse input terminal, a reset input terminal and Q and Q output terminals; means for electrically interconnecting said Q output terminal and said K input terminal and said Q output terminal and said J input terminal of each of said J-K flip-flop circuits; first input circuit means through which one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of one of said J-K flip-flop circuits; second input circuit means through which the other one of the pulses of each of said separated input signal pulse pairs may be applied to said clock pulse input terminal of the other one of said J-K flip-flop circuits; first, second and third NAND gate circuits each having two input and an output terminals; means for connecting said Q output terminal of one of said J-K flip-flop circuits and said Q output terminal of the otHer one of said J-K flip-flop circuits to respective said input terminals of said first of said NAND gate circuits; means for connecting said Q output terminal of said other one of said J-K flip-flop circuits and said Q output terminal of said one of said J-K flip-flop circuits to respective input terminals of said second of said NAND gate circuits; means for connecting said output terminal of each of said first and second NAND gate circuits to respective said input terminals of said third of said NAND gate circuits; output circuit means through which said output terminal of each of said first and second NAND gate circuits may be connected to external circuitry; first and second monostable multivibrator circuits each having an input and an output terminals; means for connecting said output terminal of said third NAND gate circuit to said input terminal of one of said monostable multivibrator circuits; means for connecting said output terminal of said one of said monostable multivibrator circuits to said input terminal of the other one of said monostable multivibrator circuits; and means for connecting said output terminal of said other one of said monostable multivibrator circuits to said reset input terminal of both of said first and second J-K flip-flop circuits.