US3205438A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase detector employing bistable circuits
Assignee: Electro Mechanical Research Inc
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Filing: 1962-01-22
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Granted: 1965-09-07
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Expires: 1982-01-22
Abstract
No abstract record available.
Inventors
- 👤 Edwin H Buck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:45
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
167 words
A PHASE DETECTOR FOR COMPARING A PAIR OF INPUT SIGNALS FOR DETERMINING DIFFERENCES IN TIMING THEREBETWEEN COMPRISING: A FIRST BISTABLE CIRCUIT WHICH IS SET TO ONE OF ITS STABLE STATES BY A FIRST OF THE INPUT SIGNALS AND TO THE OTHER OF ITS STABLE STATED BY THE SECOND OF THE INPUTT SIGNALS; CIRCUIT MEANS FOR COMPARING THE ALTERATIONS OF THE FIRST BISTABLE CIRCUIT WITH ONE OF THE INPUT SIGNALS FOR PRODUCING A CONTROL SIGNAL WHEN ONE OF THE INPUT SIGNALS BEARS A PREDETERMINED TIMING RELATION TO THE OTHER OF THE INPUT SIGNALS; A SECOND BISTABLE CIRCUIT WHICH IS SET TO ONE OF ITS STABLE STATES BY THE CONTROL SIGNAL AND TO THE OTHER OF ITS STABLE STATES BY ONE OF THE INPUT SIGNALS; AND CIRCUIT MEANS COUPLED TO THE BISTABLE CIRCUITS FOR PRODUCING AN OUTPUT SIGNAL COMPONENT HAVING A POLARITY AND A MAGNITUDE WITH RESPECT TO A PREDETERMINED REFERENCE LEVEL WHICH IS REPRESENTATIVE OF THE DIRECTION AND MAGNITUDE OF DIFFERENCES IN TIMING BETWEEN THE TWO INPUT SIGNALS.
Claim 2
Dependent Claim
167 words
A PHASE DETECTOR FOR COMPARING A PAIR OF INPUT SIGNALS FOR DETERMINING DIFFERENCES IN TIMING THEREBETWEEN COMPRISING: A FIRST BISTABLE CIRCUIT WHICH IS SET TO ONE OF ITS STABLE STATES BY A FIRST OF THE INPUT SIGNALS AND TO THE OTHER OF ITS STABLE STATED BY THE SECOND OF THE INPUTT SIGNALS; CIRCUIT MEANS FOR COMPARING THE ALTERATIONS OF THE FIRST BISTABLE CIRCUIT WITH ONE OF THE INPUT SIGNALS FOR PRODUCING A CONTROL SIGNAL WHEN ONE OF THE INPUT SIGNALS BEARS A PREDETERMINED TIMING RELATION TO THE OTHER OF THE INPUT SIGNALS; A SECOND BISTABLE CIRCUIT WHICH IS SET TO ONE OF ITS STABLE STATES BY THE CONTROL SIGNAL AND TO THE OTHER OF ITS STABLE STATES BY ONE OF THE INPUT SIGNALS; AND CIRCUIT MEANS COUPLED TO THE BISTABLE CIRCUITS FOR PRODUCING AN OUTPUT SIGNAL COMPONENT HAVING A POLARITY AND A MAGNITUDE WITH RESPECT TO A PREDETERMINED REFERENCE LEVEL WHICH IS REPRESENTATIVE OF THE DIRECTION AND MAGNITUDE OF DIFFERENCES IN TIMING BETWEEN THE TWO INPUT SIGNALS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-09-06 | 1969-03-08 | 1969-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-09-06 | 1973-03-08 | 1973-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-09-06 | 1977-03-08 | 1977-09-07 | $7700.00 | Window Closed / Lapsed |