Dead zone phase detector

Claim 2

A phase detector circuit with a dead zone in its transfer characteristic for comparing the phase of an input signal to that of a reference signal and producing a signal at its output which is related to the comparison, comprising: a first means for comparing the reference signal and the input signal, and producing output signals related to the phase difference between the compared signals, said first means comprising means for selecting a portion of the period of the compared signals and means for generating a control signal when one of the compared signals occurs during the selected portion of the other; a second means responsive to the control signal of said first means for inhibiting the output signals of said first means when one of the compared signals occurs in the selected portion of the other; and a third means for combining the output signals of said first means and producing the circuit output signal, said circuit output signal being indicative of the phase difference between the input and reference signals when the difference is greater than a predetermined minimum and zero when the difference is less than the predetermined minimum.

Claim 3

A phase detector circuit with a dead zone in its transfer characteristic for comparing the phase of an input signal at its first input terminal to that of a reference signal at its second input terminal and producing an output signal at its output terminal which is related to the comparison, comprising: a pulse spacing means for generating first, second and third repetitive output signals at first, second, and third output terminals, respectively, in response to the reference signal, the first signal leading the second in time by a first predetermined amount and the second signal leading the third in time by a second predetermine amount; a first bistable multivibrator having its SET input connected to the first output terminal of said pulse spacing means and its RESET input connected to the second output terminal of said pulse spacing means; a second bistable multivibrator having its SET input connected to the third output terminal of said pulse spacing means and its RESET input connected to the first output terminal of said pulse spacing means; a first two-input AND gate having its first input connected to the output of said first bistable multivibrator and its second input connected to the first input terminal of the circuit; a second two-input AND gate having its first input connected to the output of said second bistable multivibrator and its second input connected to the first input terminal of the cirCuit; a first pulse stretching means for generating a pulse at its output which is wider than the pulse at its input, said pulse stretching means having its input connected to the output of said first AND gate; a second pulse stretching means for generating a pulse at its output which is wider than the pulse at its input, said pulse stretching means having its input connected to the output of said second AND gate; and an amplifier with inverting and noninverting inputs having its inverting input connected to the output of said first pulse stretching means, its noninverting input connected to the output of said second pulse stretching means, and its output connected to the circuit output.

Claim 4

A phase detector circuit with a dead zone in its transfer characteristic for comparing the phase of an input signal at its first input terminal to that of a reference signal at its second input terminal and producing an output signal at its output terminal which is related to the comparison, comprising: a pulse spacing means for generating first, second and third repetitive output signals at first, second, and third output terminals, respectively, in response to the reference signal, the first signal leading the second in time by a first predetermined amount and the second signal leading the third in time by a second predetermine amount; a first bistable multivibrator having its SET input connected to the first output terminal of said pulse spacing means and its RESET input connected to the second output terminal of said pulse spacing means; a second bistable multivibrator having its SET input connected to the third output terminal of said pulse spacing means and its RESET input connected to the first output terminal of said pulse spacing means; a first two-input AND gate having its first input connected to the output of said first bistable multivibrator and its second input connected to the first input terminal of the circuit; a second two-input AND gate having its first input connected to the output of said second bistable multivibrator and its second input connected to the first input terminal of the cirCuit; a first pulse stretching means for generating a pulse at its output which is wider than the pulse at its input, said pulse stretching means having its input connected to the output of said first AND gate; a second pulse stretching means for generating a pulse at its output which is wider than the pulse at its input, said pulse stretching means having its input connected to the output of said second AND gate; and an amplifier with inverting and noninverting inputs having its inverting input connected to the output of said first pulse stretching means, its noninverting input connected to the output of said second pulse stretching means, and its output connected to the circuit output.

Claim 5

A circuit as claimed in claim 2 wherein said pulse spacing means is a delay line with three output taps, each tap corresponding to a greater time delay from the input than the preceding tap.

Claim 6

A circuit as claimed in claim 2 wherein the reference signal has a significantly higher frequency than the test signal and the pulse spacing means comprises: a multiple output counter circuit whose outputs indicate the number of pulses applied to its input since the last time it was reset; a first decoder circuit responsive to the outputs of said counter circuit for resetting the counter at such a rate that one of its outputs is at a frequency substantially the same as the detector circuit input signal; a second decoder circuit responsive to the output of said counter circuit for producing an output when the outputs of said counter circuit indicate that a first preselected number of pulses have been applied to said counter circuit''s input; a third decoder circuit responsive to the outputs of said counter circuit for producing an output when the outputs of said counter circuit indicate that a second preselected number of pulses have been applied to said counter circuit''s input, the second preselected number being larger than the first; and a fourth decoder circuit responsive to the outputs of said counter circuit for producing an output when the outputs of said counter circuit indicate that a third preselected number of pulses have been applied to said counter circuit''s input, the third preselected number being larger than the second.

Claim 7

A circuit as claimed in claim 2 wherein said first and second pulse stretching means are monostable multivibrators arranged to have output pulses that are wider than the pulses of the detector circuit input signal.

Claim 8

A phase detector circuit with a dead zone in its transfer characteristic for comparing the phase of an input signal at its first input terminal to that of a reference signal at its second input terminal and producing an output signal at its output terminal which is related to the comparison, comprising: a first delaying means, having the second input terminal of the circuit connected to its input, for producing the reference signal delayed by a first time period at its output; a second delaying means having the first input terminal of the circuit connected to its input, for producing the input signal delayed by the first time period at its output; a first bistable multivibrator having its SET input connected to the output of said first delaying means; a second bistable multivibrator having its SET input connected to the output of said second delaying means; a two-input AND gate having the outputs of said first and second bistable multivibrators connected to its first and second inputs, respectively; a third delaying means, for delaying signals applied to it by a second time period, connected between the output of said AND gate and the RESET inputs of said first and second bistable multivibrator; a first monostable multivibrator having its input connected to the second input terminal of the circuit, for producing a pulse of predetermined width at its output in response to the signal at its input; a second monostable multivibrator having its inPut connected to the first input terminal of the circuit, for producing a pulse of predetermined width at its output in response to the signal at its input; a first INHIBIT gate having its SIGNAL input connected to the output of said first bistable multivibrator and its INHIBIT input connected to the output of said first monostable multivibrator, for passing the level at its SIGNAL input only when the level at its INHIBIT input is low; a second INHIBIT gate having its SIGNAL input connected to the output of said second bistable multivibrator and its INHIBIT input connected to the output of said second monostable multivibrator, for passing the level at its SIGNAL input only when the level at its INHIBIT input is low; an amplifier with inverting and noninverting inputs having its inverting input connected to the output of said first INHIBIT gate and its noninverting input connected to the output of said second INHIBIT gate; and a low-pass filter connected between the output of said amplifier and the circuit output.

Claim 9

A phase detector circuit with a dead zone in its transfer characteristic for comparing the phase of an input signal at its first input terminal to that of a reference signal at its second input terminal and producing an output signal at its output terminal which is related to the comparison, comprising: a first delaying means, having the second input terminal of the circuit connected to its input, for producing the reference signal delayed by a first time period at its output; a second delaying means having the first input terminal of the circuit connected to its input, for producing the input signal delayed by the first time period at its output; a first bistable multivibrator having its SET input connected to the output of said first delaying means; a second bistable multivibrator having its SET input connected to the output of said second delaying means; a two-input AND gate having the outputs of said first and second bistable multivibrators connected to its first and second inputs, respectively; a third delaying means, for delaying signals applied to it by a second time period, connected between the output of said AND gate and the RESET inputs of said first and second bistable multivibrator; a first monostable multivibrator having its input connected to the second input terminal of the circuit, for producing a pulse of predetermined width at its output in response to the signal at its input; a second monostable multivibrator having its inPut connected to the first input terminal of the circuit, for producing a pulse of predetermined width at its output in response to the signal at its input; a first INHIBIT gate having its SIGNAL input connected to the output of said first bistable multivibrator and its INHIBIT input connected to the output of said first monostable multivibrator, for passing the level at its SIGNAL input only when the level at its INHIBIT input is low; a second INHIBIT gate having its SIGNAL input connected to the output of said second bistable multivibrator and its INHIBIT input connected to the output of said second monostable multivibrator, for passing the level at its SIGNAL input only when the level at its INHIBIT input is low; an amplifier with inverting and noninverting inputs having its inverting input connected to the output of said first INHIBIT gate and its noninverting input connected to the output of said second INHIBIT gate; and a low-pass filter connected between the output of said amplifier and the circuit output.