US5159574A
Expired / Lapsed
US
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Address transition detection circuit
Assignee: SK Hynix Inc
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Filing: 1991-11-26
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Granted: 1992-10-27
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Expires: 2011-11-26
Abstract
Abstract The present invention provides an address transition detection circuit comprising inverting means (11 and G12 through G14) and a MOSFET's circuit which is composed of two cross-coupled MOSFET's (MN5 and MN6), first and second MOSFET's (MP2 and MP3) connected in series with each other, and third and fourth MOSFET's (MP4 and MP5) connected in series with each other, wherein the output lines of each inverter within the inverting means.
Inventors
- 👤 Young H. Kim
- 👤 Hong S. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:43
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
228 words
An address transition detection circuit in a memory device, comprising: an address input line; a first inverter connected to the address input line; a second inverter connected to the first inverter; a delay circuit connected to the second inverter; a third inverter connected to the delay circuit; a first p channel MOSFET and a second p channel MOSFET connected in series with each other, in which the gate of the first p channel MOSFET is connected to the address input line and the gate of the second p channel MOSFET is connected to the output line of the third inverter; a third p channel MOSFET and a fourth p channel MOSFET connected in serial with each other, in which the gate of the third p channel MOSFET is connected to the output line of the first inverter and the gate of the fourth p channel MOSFET is connected to the output line of the delay circuit; and a first n channel MOSFET and a second n channel MOSFET cross-coupled with each other, in which the drains thereof respectively connected to the drains of the second and the fourth p channel MOSFET's, the source of the first n channel MOSFET is connected to the output line of the first inverter, and the source of the second n channel MOSFET is connected to the output line of the delay circuit.
Claim 2
Dependent Claim
228 words
An address transition detection circuit in a memory device, comprising: an address input line; a first inverter connected to the address input line; a second inverter connected to the first inverter; a delay circuit connected to the second inverter; a third inverter connected to the delay circuit; a first p channel MOSFET and a second p channel MOSFET connected in series with each other, in which the gate of the first p channel MOSFET is connected to the address input line and the gate of the second p channel MOSFET is connected to the output line of the third inverter; a third p channel MOSFET and a fourth p channel MOSFET connected in serial with each other, in which the gate of the third p channel MOSFET is connected to the output line of the first inverter and the gate of the fourth p channel MOSFET is connected to the output line of the delay circuit; and a first n channel MOSFET and a second n channel MOSFET cross-coupled with each other, in which the drains thereof respectively connected to the drains of the second and the fourth p channel MOSFET's, the source of the first n channel MOSFET is connected to the output line of the first inverter, and the source of the second n channel MOSFET is connected to the output line of the delay circuit.
Claim 3
Dependent Claim
229 words
An address transition detection circuit in a memory device, comprising: an address input line; a first inverter connected to the address input line; a second inverter connected to the first inverter; a delay circuit connected to the second inverter; a third inverter connected to the delay circuit; a first n channel MOSFET and a second n channel MOSFET connected in serial with each other, in which the gate of the first n channel MOSFET is connected to the address input line and the gate of the second n channel MOSFET is connected to the output line of the third inverter; a third n channel MOSFET and a fourth n channel MOSFET connected in series with each other, in which the gate of the third n channel MOSFET is connected to the output line of the first inverter and the gate of the fourth n channel MOSFET is connected to the output line of the delay circuit; and a first p channel MOSFET and a second p channel MOSFET cross-coupled with each other, in which the drains thereof are respectively connected to the drains of the first and the third n channel MOSFET's, the source of the first p channel MOSFET is connected to the output line of the first inverter, and the source of the second p channel MOSFET is connected to the output line of the delay circuit.
Claim 4
Dependent Claim
229 words
An address transition detection circuit in a memory device, comprising: an address input line; a first inverter connected to the address input line; a second inverter connected to the first inverter; a delay circuit connected to the second inverter; a third inverter connected to the delay circuit; a first n channel MOSFET and a second n channel MOSFET connected in serial with each other, in which the gate of the first n channel MOSFET is connected to the address input line and the gate of the second n channel MOSFET is connected to the output line of the third inverter; a third n channel MOSFET and a fourth n channel MOSFET connected in series with each other, in which the gate of the third n channel MOSFET is connected to the output line of the first inverter and the gate of the fourth n channel MOSFET is connected to the output line of the delay circuit; and a first p channel MOSFET and a second p channel MOSFET cross-coupled with each other, in which the drains thereof are respectively connected to the drains of the first and the third n channel MOSFET's, the source of the first p channel MOSFET is connected to the output line of the first inverter, and the source of the second p channel MOSFET is connected to the output line of the delay circuit.
References Cited (Backward Citations)
US4592028A
Cited
US4843596A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |