Abstract A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.
A semiconductor memory device receiving an address signal providing data on an I/O line, said memory device comprising: a first detection circuit for detecting an address transition and for generating a short-width first pulse signal in response; a column decoder-activating signal generator for detecting the start of generation of said first pulse signal and for generating a column decoder-activating signal in response; a second detection circuit for detecting the conclusion of said first pulse signal and for generating a second pulse siganl in response; a preamplifier-activating signal generator for generating a preamplifier-activating signal to activate a preamplifier which amplifies and latches the data on said I/O line upon receipt of said second pulse signal; and a reset signal generator for generating a reset signal to deactivate said column decoder-activating signal and to delay said preamplifier-activating signal; said preamplifier-activating signal generator and said reset signal generator being reset while said first pulse signal is output.
Claim 2
Dependent Claim
154 words
A semiconductor memory device receiving an address signal providing data on an I/O line, said memory device comprising: a first detection circuit for detecting an address transition and for generating a short-width first pulse signal in response; a column decoder-activating signal generator for detecting the start of generation of said first pulse signal and for generating a column decoder-activating signal in response; a second detection circuit for detecting the conclusion of said first pulse signal and for generating a second pulse siganl in response; a preamplifier-activating signal generator for generating a preamplifier-activating signal to activate a preamplifier which amplifies and latches the data on said I/O line upon receipt of said second pulse signal; and a reset signal generator for generating a reset signal to deactivate said column decoder-activating signal and to delay said preamplifier-activating signal; said preamplifier-activating signal generator and said reset signal generator being reset while said first pulse signal is output.