Page-in, burst-out FIFO

Claim 2

A FIFO system for interfacing a system bus, including an address bus and a data bus, to a DRAM, with the DRAM operating in a normal access mode and a page mode, with data transferred at a higher page mode rate in the page mode, and with each storage location in the DRAM specified by a row address and a column address, said system comprising: a data register having an input coupled to said data bus and an output coupled to a data input of the DRAM; an address register, having an input coupled to said address bus and an output coupled to an address input of the DRAM; a write control unit, coupled to said data and address registers, for writing page data having a first row address into said data register and writing column addresses of said page data into said address register; and a read control unit, coupled to said data and address registers, for initiating a read operation to provide said page data to the data input of said DRAM and said column addresses to the address input of said DRAM at the page mode rate when the number of page data stored in said data register exceeds a predetermined number; and a page change detection unit, coupled to said address bus and said read control unit, for initiating a read operation when a second row address transmitted on said address bus is different from the first row address of the page data stored in said data register.

Claim 3

The system of claim 1 wherein said page change detection unit comprises: a row address latch, having an input coupled to said address bus, for latching said first address; a comparator, having a first input coupled to an output of said row address latch, a second input coupled to said address bus to receive a second address transmitted on said bus, and an output for asserting a read operation initiation signal when said first and second addresses are not the same.

Claim 4

A FIFO system for interfacing a system bus, including an address bus and a data bus, to a DRAM, with the DRAM operating in a normal access mode and a page mode, with data transferred at a higher page mode rate in the page mode, and with each storage location in the DRAM specified by a row address and a column address, said system comprising: a data register having an input coupled to said data bus and an output coupled to a data input of the DRAM; an address register, having an input coupled to said address bus and an output coupled to an address input of the DRAM; a write control unit, coupled to said data and address registers, for writing page data having a first row address into said data register and writing column addresses of said page data into said address register; a read control unit, coupled to said data and address registers, for initiating a read operation to provide said page data to the data input of said DRAM and said column addresses to the address input of said DRAM at the page mode rate when the number of page data stored in said data register exceeds a predetermined number; and a write counter, having an input coupled to receive a write clock signal including a series of write pulses and an output for providing a write count value to said data and address register, for incrementing a write count value when a write pulse is received, where said data register writes data to a location specified by said write count value and said address register writes a column address to a location specified by said write count value; and wherein said read control unit comprises: a read counter, having an input coupled to receive a read clock signal including a series of read pulses and an output for providing a read count value to said data and address register, for incrementing a read count value when a read pulse is received, where said data register reads data from a location specified by said read count value and said address register reads a column address from a location specified by said read count value.

Claim 5

A FIFO system for interfacing a system bus, including an address bus and a data bus, to a DRAM, with the DRAM operating in a normal access mode and a page mode, with data transferred at a higher page mode rate in the page mode, and with each storage location in the DRAM specified by a row address and a column address, said system comprising: a data register having an input coupled to said data bus and an output coupled to a data input of the DRAM; an address register, having an input coupled to said address bus and an output coupled to an address input of the DRAM; a write control unit, coupled to said data and address registers, for writing page data having a first row address into said data register and writing column addresses of said page data into said address register; a read control unit, coupled to said data and address registers, for initiating a read operation to provide said page data to the data input of said DRAM and said column addresses to the address input of said DRAM at the page mode rate when the number of page data stored in said data register exceeds a predetermined number; and a write counter, having an input coupled to receive a write clock signal including a series of write pulses and an output for providing a write count value to said data and address register, for incrementing a write count value when a write pulse is received, where said data register writes data to a location specified by said write count value and said address register writes a column address to a location specified by said write count value; and wherein said read control unit comprises: a read counter, having an input coupled to receive a read clock signal including a series of read pulses and an output for providing a read count value to said data and address register, for incrementing a read count value when a read pulse is received, where said data register reads data from a location specified by said read count value and said address register reads a column address from a location specified by said read count value.