FIFO memory system

Claim 2

A FIFO memory system comprising: a RAM memory; a write pointer register for storing a minimum change coded address of the next data element to be written into said RAM memory; a read pointer register for storing a minimum change coded address of the next data element to be read from said RAM memory; an offset generator for comparing the contents of said registers, and generating at an output thereof an offset signal representing the amount of memory space occupied; a programmable offset register for providing a programmed offset signal; and a comparator for comparing said offset signal and said programmed offset signal, and providing a ready signal when said offset signal is greater than or equal to said programmed offset signal.

Claim 3

The FIFO memory system of claim 1 wherein said write pointer register includes first means for incrementing said register in response to a write signal received thereby, and said read pointer register includes second means for incrementing said register in response to a read signal received thereby.

Claim 4

The FIFO memory system of claim 3 wherein said write signal has a leading and trailing edge and wherein said first means includes means responsive to said trailing edge.

Claim 5

The FIFO memory system of claim 3 wherein said RAM memory has means for writing data into said RAM memory in response to the reading edge of said write signal.

Claim 6

The FIFO memory system of 2 wherein said read signal has a leading and trailing edge and wherein said second means includes means responsive to said trailing edge.

Claim 7

The FIFO memory system of 2 wherein said read signal has a leading and trailing edge and wherein said second means includes means responsive to said trailing edge.

Claim 8

The FIFO memory system of claim 5 wherein said RAM memory has means for reading data from said RAM memory in response to the loading edge of said read signal.

Claim 9

The FIFO memory system of claim 1 wherein said programmable offset register means for receiving a binary coded programmed offset signal, said system further comprising: a binary to minimum change converter connecting said offset register to said comparator for providing said programmed offset signal to said comparator.

Claim 10

The FIFO memory system of claim 1 wherein said programmable offset register includes means for loading said register with said programmed offset signal.

Claim 11

The FIFO memory system of claim 8 wherein said RAM memory has an input data bus for writing data to said memory, and wherein said loading means includes a connection between said bus and said offset register.

Claim 12

The FIFO memory system of claim 9 wherein said loading means further includes a control line for enabling the loading of said programmable offset register.

Claim 13

The FIFO memory system of claim 10 wherein said programmable offset register includes a plurality of D type flip-flops, each flipflop having D and CK input ports and a Q output, wherein said D input ports are connected to respective lines in said input data bus, and said CK ports are connected to said control line.

Claim 14

The FIFO memory system of claim 1 wherein said RAM memory is a dual ported RAM having input and output data busses for writing data to and reading data from, respectively, said RAM memory.

Claim 15

The FIFO memory system of claim 1 wherein said offset generator includes means for performing in minimum change code an equivalent binary subtraction.

Claim 16

The FIFO memory system of claim 1 wherein said comparator includes: a wrap around detector for receiving said offset signal, monitoring changes in said offset signal, determining if the RAM memory is full or empty when said offset is zero, and generating at an output thereof a wrap signal indicating full or empty; a circuit for receiving said offset signal and programmed offset signal, determining when said offset signal is greater than or equal to said programmed offset signal, and generating at an output thereof a greater than or equal to signal; and a flag generator connected to the outputs of said wrap around detector, said circuit, and said offset generator for providing said ready signal.

Claim 17

The FIFO memory system of 14 wherein said flag generator includes mean for providing a full or empty signal indicating said RAM memory is full or empty, respectively.

Claim 18

The FIFO memory system of 14 wherein said flag generator includes mean for providing a full or empty signal indicating said RAM memory is full or empty, respectively.

Claim 19

The FIFO memory system of claim 14 wherein said wrap around detector includes a NAND gate and a D-type flip-flop having D and CK ports and a Q output port; wherein said D input port is connected to a single data bit line from the output of said offset generator, the inputs to said NAND gate are connected to a plurality of other data bit lines from the output of said offset generator, the output of said NAND gate is connected to said CK input port, and said Q output port provides said wrap signal.

Claim 20

The FIFO memory system of claim 14 wherein said flag generator includes an AND gate and a NOR gate, said AND gate receiving as inputs the inverse of said wrap and offset signals, said NOR gate receives as inputs the output of said AND gate and the inverse of said greater than or equal to signal.

Claim 21

A FIFO memory system comprising: a RAM memory; a write pointer register for storing a minimum change coded address of the next data element to be written into said RAM memory, said write pointer register including first means for incrementing said register in response to a write signal received thereby; a read pointer register for storing a minimum change coded address of the next data element to be read from said RAM memory, said read pointer register including second means for incrementing said register in response to a read signal received thereby; an offset generator for comparing the contents of said registers, and generating at an output thereof an offset signal representing the amount of memory space occupied; a programmable offset register for providing a programmed offset signal, said register including means for loading said register with said programmed offset signal; and a comparator for comparing said offset signal and said programmed offset signal, and providing a ready signal when said offset signal is greater than or equal to said programmed offset signal; wherein said comparator includes: a wrap around detector for receiving said offset signal, monitoring changes in said offset signal, determining if the RAM memory is full or empty when said offset is zero, and generating at an output thereof a wrap signal indicating full or empty; a circuit for receiving said offset signal and programmed offset signal, determining when said offset signal is greater than or equal to said programmed offset signal, and generating at an output thereof a greater than or equal to signal; and a flag generator connected to the outputs of said wrap around detector, said circuit, and said offset generator for providing said ready signal.

Claim 22

A FIFO memory system comprising: a RAM memory; a write pointer register for storing a minimum change coded address of the next data element to be written into said RAM memory, said write pointer register including first means for incrementing said register in response to a write signal received thereby; a read pointer register for storing a minimum change coded address of the next data element to be read from said RAM memory, said read pointer register including second means for incrementing said register in response to a read signal received thereby; an offset generator for comparing the contents of said registers, and generating at an output thereof an offset signal representing the amount of memory space occupied; a programmable offset register for providing a programmed offset signal, said register including means for loading said register with said programmed offset signal; and a comparator for comparing said offset signal and said programmed offset signal, and providing a ready signal when said offset signal is greater than or equal to said programmed offset signal; wherein said comparator includes: a wrap around detector for receiving said offset signal, monitoring changes in said offset signal, determining if the RAM memory is full or empty when said offset is zero, and generating at an output thereof a wrap signal indicating full or empty; a circuit for receiving said offset signal and programmed offset signal, determining when said offset signal is greater than or equal to said programmed offset signal, and generating at an output thereof a greater than or equal to signal; and a flag generator connected to the outputs of said wrap around detector, said circuit, and said offset generator for providing said ready signal.

Claim 23

The FIFO memory system of claim 18 wherein said programmable offset register includes means for receiving a binary coded programmed offset signal, said system further comprising: a binary to minimum change code converter connecting said offset register to said comparator for providing said programmed offset signal to said comparator.

Claim 24

The FIFO memory system of claim 19 wherein: said write and read signals each has a leading and trailing edge; said first means includes means responsive to the trailing edge of said write signal; said RAM memory has means for writing data into said RAM memory in response to the leading edge of said write signal; said second means includes means responsive to the trailing edge of said read signal; said RAM memory has means for reading data from said RAM memory in response to the leading edge of said read signal.

Claim 25

The FIFO memory system of claim 20 wherein said offset generator includes means for performing in minimum change code an equivalent binary subtraction.

Claim 26

A FIFO memory system comprising: a RAM memory; a write pointer register for storing the address of the next data element to be written into said RAM memory; a read pointer register for storing the address of the next data element to be read from said RAM memory; an offset generator for comparing the contents of said registers, and generation output thereof an offset signal representing the amount of memory space occupied; a programmable offset register for providing a programmed offset signal; and a comparator for comparing said offset signal and said programmed offset signal, and providing a ready signal when said offset signal is greater than or equal to said programmed offset signal.

Claim 27

A FIFO memory system comprising: a RAM memory; a write pointer register for storing the address of the next data element to be written into said RAM memory; a read pointer register for storing the address of the next data element to be read from said RAM memory; an offset generator for comparing the contents of said registers, and generation output thereof an offset signal representing the amount of memory space occupied; a programmable offset register for providing a programmed offset signal; and a comparator for comparing said offset signal and said programmed offset signal, and providing a ready signal when said offset signal is greater than or equal to said programmed offset signal.

Claim 28

The FIFO memory system of claim 22 wherein said comparator includes: a wrap around detector for receiving said offset signal, monitoring changes in said offset signal, determining if the RAM memory is full or empty when said offset is zero, and generating at an output thereof a wrap signal indicating full or empty; a circuit for receiving said offset signal and programmed offset signal, determining when said offset signal is greater than or equal to said programmed offset signal, and generating at an output thereof a greater than or equal to signal; and a flag generator connected to the outputs of said wrap around detector, said circuit, and said offset generator for providing said ready signal.

Claim 31

The method of claim 24 further comprising: reading the contents of said RAM memory; and incrementing said read pointer in response to the reading of said RAM memory.

Claim 32

The method of claim 24 wherein said step of comparing the contents of said write and read pointers comprises: performing in minimum change code an equivalent binary subtraction of the contents of said pointers thereby generating a minimum change coded offset value.

Claim 33

The method of claim 24 wherein said step of comparing said offset value with said programmed offset value comprises: monitoring changes in said offset value; determining if the RAM memory is full or empty when the offset value is zero; and generating a full or empty signal indicating the RAM memory is full or empty, respectively, when the offset value is zero.

Claim 34

The method of claim 24 wherein said step of comparing said offset value with said programmed offset value comprises: determining when said offset value is greater than or equal to said programmed offset value; generating a signal indicating when said offset value is greater than or equal to said programmed offset value.

Claim 39

The method of claim 30 further comprising: reading the contents of said RAM memory; and incrementing said read pointer in response to the reading of said RAM memory.

Claim 40

The method of claim 30 wherein said step of comparing the contents of said write and read pointers comprises: subtracting the contents of said pointers thereby generating an offset value.

Claim 41

The method of claim 30 wherein said step of comparing said offset value with said programmed offset value comprises: monitoring changes in said offset value; determining if the RAM memory is full or empty when the offset value is zero; and generating a full or empty signal indicating the RAM memory is full or empty, respectively, when the offset value is zero.

Claim 42

The method of claim 30 wherein said step of comparing said offset value with said programmed offset value comprises: determining when said offset value is greater than or equal to said programmed offset value; generating a signal indicating when said offset value is greater than or equal to said programmed offset value.