US5327393A
Expired / Lapsed
US
⏱️ 0.0 years remaining
External memory interface circuit capable of carrying out initialization of external memory with a reduced initialization time duration
Assignee: NEC Corp
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Filing: 1993-05-27
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Granted: 1994-07-05
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Expires: 2013-05-27
Abstract
Abstract In an external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory, the external memory interface circuit carries out initialization of the external memory on reception of a clear signal. In the initialization, an end address detecting circuit detects an end address of an address signal generated by an address generator and produces an end address detection signal. A signal generating circuit continuously generates an enable signal, a write-in pulse signal, and an address increment pulse signal until the signal generating circuit receives the end address detection signal after reception of the clear signal. A reset signal generating circuit generates an address reset signal on reception of the enable signal. A write-in register successively produces zero data while the write-in register receives the enable signal to write the zero data in the external memory in synchronism with the write-in pulse signal. The address register produces address zero on reception of the address reset signal and increasing the address of the external memory one by one in response to the address increment pulse signal.
Inventors
- 👤 Mitsuhiro Koyanagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:10
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
327 words
An external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory connected to said signal processing circuit, said signal processing circuit comprising clear signal generating means for generating a clear signal designating initialization of said external memory, said external memory interface circuit being connected to said clear signal generating means and comprising an address register for producing an address signal representing an address of said external memory at a time to supply said address signal to said external memory and a write-in register for writing said input signal in said external memory, said external memory interface circuit carrying out said initialization of said external memory on reception of said clear signal and further comprising: end address detecting means connected to said address register for detecting an end address of said address signal to produce an end address detection signal; signal generating means connected to said clear signal generating means and said end address detecting means for continuously generating an enable signal, a write-in pulse signal, and an address increment pulse signal until said signal generating means receives said end address detection signal after reception of said clear signal, said signal generating means supplying said enable signal, said write-in pulse signal, and said address increment pulse signal to said write-in register, said external memory, and said address register, respectively; and reset signal generating means connected to said signal generating means for generating an address reset signal on reception of said enable signal to supply said address reset signal to said address register; said write-in register successively producing zero data while said write-in register receives said enable signal to successively write said zero data in said external memory in synchronism with said write-in pulse signal, said address register producing address zero on reception of said address reset signal and increasing said address of said external memory one by one in response to said address increment pulse signal.
Claim 2
Dependent Claim
327 words
An external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory connected to said signal processing circuit, said signal processing circuit comprising clear signal generating means for generating a clear signal designating initialization of said external memory, said external memory interface circuit being connected to said clear signal generating means and comprising an address register for producing an address signal representing an address of said external memory at a time to supply said address signal to said external memory and a write-in register for writing said input signal in said external memory, said external memory interface circuit carrying out said initialization of said external memory on reception of said clear signal and further comprising: end address detecting means connected to said address register for detecting an end address of said address signal to produce an end address detection signal; signal generating means connected to said clear signal generating means and said end address detecting means for continuously generating an enable signal, a write-in pulse signal, and an address increment pulse signal until said signal generating means receives said end address detection signal after reception of said clear signal, said signal generating means supplying said enable signal, said write-in pulse signal, and said address increment pulse signal to said write-in register, said external memory, and said address register, respectively; and reset signal generating means connected to said signal generating means for generating an address reset signal on reception of said enable signal to supply said address reset signal to said address register; said write-in register successively producing zero data while said write-in register receives said enable signal to successively write said zero data in said external memory in synchronism with said write-in pulse signal, said address register producing address zero on reception of said address reset signal and increasing said address of said external memory one by one in response to said address increment pulse signal.
Claim 3
Dependent Claim
115 words
An external memory interface circuit as claimed in claim 1, wherein said signal generating means comprises: a flip-flop circuit connected to said clear signal generating means and said end address detecting means for continuously producing a flip-flop output signal as said enable signal until said flip-flop circuit receives said end address detection signal after reception of said clear signal; and a counter connected to said flip-flop circuit and supplied with a clock pulse signal consisting of a sequence of clock pulses for counting said sequence of clock pulses while said counter circuit receives said flip-flop output signal to produce first and second count signals as said write-in pulse and said address increment pulse signals, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |