Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same

Claim 2

A clock generating circuit comprising: a delay circuit for delaying an input clock signal and outputting the delayed input clock signal, said delay circuit including a plurality of delay units for delaying said input clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), and said first unit delay amount changing in accordance with a drive potential of said plurality of delay units; a phase comparator circuit for making a comparison between phases of said input clock signal and the output signal of said delay circuit; a drive potential control circuit for controlling said drive potential in response to a result of phase comparison of said phase comparator circuit; and a delay control circuit for controlling said L in response to said result of phase comparison.

Claim 3

The clock generating circuit according to claim 1 , wherein said drive potential control circuit includes: a potential regulator circuit for controlling said drive potential to a reference potential; and a reference potential generating circuit for controlling said reference potential in response to said result of phase comparison.

Claim 4

The clock generating circuit according to claim 1 , further comprising: a delay unit fixing circuit arranged between said phase comparator circuit and said delay control circuit for stopping transmission of said result of phase comparison to said delay control circuit in response to activation of a first control signal; a drive potential fixing circuit arranged between said phase comparator circuit and said drive potential control circuit for stopping transmission of said result of phase comparison to said drive potential control circuit in response to activation of a second control signal; and a control circuit for producing said first and second control signals.

Claim 5

The clock generating circuit according to claim 3 , wherein said control circuit activates and inactivates said first and second control signals, respectively, and synchronizes said input signal with the output signal of said delay circuit by the control of said drive potential in response to said phase comparison result.

Claim 6

The clock generating circuit according to claim 4 , wherein said control circuit changes said L in response to said result of phase comparison by inactivating said first control signal and activating said second control signal, and thereafter performs activation of said first control signal and inactivation of said second control signal, if said input signal is not synchronized with the output signal of said delay circuit even when said drive potential reaches either the upper or lower limit of an available range.

Claim 7

The clock generating circuit according to claim 3 , wherein said control circuit activates at least one of said first and second control signals.

Claim 8

The clock generating circuit according to claim 1 , wherein each of said plurality of delay units has a plurality of inverters operating with said drive potential.

Claim 9

The clock generating circuit according to claim 1 , wherein said delay circuit further includes a plurality of sub-delay units for further delaying said input signal by a second delay amount obtained by multiplying a second unit delay amount by M (M is a non-negative integer), said second unit delay amount is shorter than said first unit delay amount, and said delay control circuit controls said L and M in response to the result of said phase comparison.

Claim 10

The clock generating circuit according to claim 8 , wherein said input clock signal has two signal levels equal to a first potential and a second potential lower than said first potential, respectively, each of said plurality of sub-delay units has a switch and a capacitor connected in series between a node supplied with said input clock signal and a power supply node supplying said second potential, and said control circuit controls said M by turning on/off said switch.

Claim 11

The clock generating circuit according to claim 8 , wherein each of said plurality of delay units has a plurality of inverters operating with said drive potential, and each of said plurality of sub-delay units has a plurality of inverters operating with said drive potential and being smaller in number than said plurality of delay units.

Claim 12

The clock generating circuit according to claim 8 , further comprising: a delay unit fixing circuit arranged between said phase comparator circuit and said delay control circuit for stopping transmission of said result of phase comparison to said delay control circuit in response to activation of a first control signal; a drive potential fixing circuit arranged between said phase comparator circuit and said drive potential control circuit for stopping transmission of said result of phase comparison to said drive potential control circuit in response to activation of a second control signal; and a control circuit for producing said first and second control signals.

Claim 13

The clock generating circuit according to claim 11 , wherein said control circuit controls said first unit delay amount within a predetermined range under the control of said drive potential by activating and inactivating said first and second control signals, respectively, and thereafter controls said M in response to said result of phase comparison by inactivating and activating said first and second control signals, respectively, for synchronizing said input signal with the output signal of said delay circuit, and said predetermined range is determined such that the cycle time of said input signal is at least a product of said first unit delay amount and N (N: a natural number smaller than L−1), and is not more than a product of said first unit delay amount and (N+1).

Claim 14

The clock generating circuit according to claim 11 , wherein said control circuit activates at least one of said first and second control signals.

Claim 15

A semiconductor memory device for operation in synchronization with an external clock signal, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a data terminal for inputting and outputting data for writing and reading with respect to said memory cell array; a buffer circuit for executing data transmission between said memory cell array and said data terminal in response to an internal clock signal; and a clock generating circuit for generating said internal clock signal synchronized with said external clock signal, said clock generating circuit including a delay circuit for delaying said external clock signal to generate said internal clock signal, said delay circuit having a plurality of delay units for delaying said external clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), said first unit delay amount changing in accordance with a drive potential of said plurality of delay units, and said clock generating circuit further including, a phase comparator circuit for making a comparison between phases of said external clock signal and said internal clock signal, a drive potential control circuit for controlling said drive potential in response to a result of phase comparison of said phase comparator circuit, and a delay control circuit for controlling said L in response to said result of phase comparison.

Claim 16

A semiconductor memory device for operation in synchronization with an external clock signal, comprising: a memory cell array having a plurality of memory cells arranged in rows and columns; a data terminal for inputting and outputting data for writing and reading with respect to said memory cell array; a buffer circuit for executing data transmission between said memory cell array and said data terminal in response to an internal clock signal; and a clock generating circuit for generating said internal clock signal synchronized with said external clock signal, said clock generating circuit including a delay circuit for delaying said external clock signal to generate said internal clock signal, said delay circuit having a plurality of delay units for delaying said external clock signal by a first delay amount obtained by multiplying a first unit delay amount by L (L: a natural number), said first unit delay amount changing in accordance with a drive potential of said plurality of delay units, and said clock generating circuit further including, a phase comparator circuit for making a comparison between phases of said external clock signal and said internal clock signal, a drive potential control circuit for controlling said drive potential in response to a result of phase comparison of said phase comparator circuit, and a delay control circuit for controlling said L in response to said result of phase comparison.

Claim 17

The semiconductor memory device according to claim 14 , wherein said clock generating circuit further includes: a delay unit fixing circuit arranged between said phase comparator circuit and said delay control circuit for stopping transmission of said result of phase comparison to said delay control circuit in response to activation of a first control signal; a drive potential fixing circuit arranged between said phase comparator circuit and said drive potential control circuit for stopping transmission of said result of phase comparison to said drive potential control circuit in response to activation of a second control signal; and a control circuit for producing said first and second control signals.

Claim 18

The semiconductor memory device according to claim 14 , wherein said delay circuit further includes a plurality of sub-delay units for further delaying said input signal by a second delay amount obtained by multiplying a second unit delay amount by M (M is a non-negative integer), said second delay amount is shorter than said first unit delay amount, and said delay control circuit controls said L and M in response to the result of said phase comparison.

Claim 19

The semiconductor memory device according to claim 16 , wherein said clock generating circuit further includes: a delay unit fixing circuit arranged between said phase comparator circuit and said delay control circuit for stopping transmission of said result of phase comparison to said delay control circuit in response to activation of a first control signal; a drive potential fixing circuit arranged between said phase comparator circuit and said drive potential control circuit for stopping transmission of said result of phase comparison to said drive potential control circuit in response to activation of a second control signal; and a control circuit for producing said first and second control signals.